Design An LNA For 38-GHz Radios

May 18, 2011
By using a well-known device model, and taking into account the limitations of on-chip passive elements, a two-stage LNA was designed with excellent mm-wave performance.

Shabbir Majeed Chaudhry and Farhat Abbas

Millimeter-wave radios at 38 GHz support a variety of communications applications, including high-data-rate point-to-point links. In support of such applications, a two-stage common-source low-noise amplifier (LNA) was developed using 90-nm RF-CMOS process technology. The wideband LNA operates from 32 to 39 GHz with peak gain of more than 14 dB and average gain of 12 dB across its frequency range. It achieves noise figure of 3 dB with excellent stability over a large power range. The reflection coefficients exceed 35 dB at 38 GHz, and the amplifier requires only 6.6 ma current per stage from a +1.4-vdC supply, making it suitable for low-power, high-data-rate applications.

Millimeter-wave circuits have attracted a great deal of attention for their available bandwidth for such applications as wireless local area networks (WLANs), satellite-communications (satcom) systems, medical imaging, and automotive radar.1

Silicon CMOS technology has made tremendous strides in recent years for linear performance at high microwave and millimeter-wave frequencies. Many device parameters have been enhanced, including transconductance (gm), minimum noise figure (NFmin), transition frequency (ft), and maximum frequency of oscillation (fmax).2 Additionally, when short-channel CMOS transistors are biased at current densities between 0.15 and 0.40 mA/m, these figures of merit (FOMs) have been reported to become almost insensitive to variations in drain current (ID) and gate-source voltage (VGS).3

At higher frequencies, the losses of passive circuit elements, such as inductors, can degrade signal gain as well as noise figure in an amplifier. Inductors and transmission lines are critical at higher frequencies, since their quality factor (Q) is rather low due to the lossy substrate material and resistance of the metal conductor.4 To achieve larger inductance values, inductors can occupy a large amount of the chip area in an integrated circuit (IC) or device. with technology scaling to reach higher frequencies, device features are miniaturized, further degrading the Q of multiconductor-transmission-line (MTL) inductors.5

A benefit of designing circuits at millimeter-wave frequencies is the reduced form factor of on-chip passive circuit elements. significant savings in chip area result from the exclusive use of spiral inductors for impedance-matching networks.6 Although the inductors are small enough to be implemented as microstrip lines over metal-1 ground planes, measurements on test structures have indicated that the spiral inductor implementation systematically leads to higher Qs while minimizing chip area.7

In the 38-GHz LNA design, the top metal is used to build the transmission lines, and the metal-1 layer is used to construct the ground plane. Because the silicon dioxide layer is very thin, this transmission line exhibited a loss of 1.3 dB/mm at 30 GHz. in order to build a high-Q inductor, the series resistance must be low and the shunt parasitic capacitance must be small. At high frequencies, the skin effect causes series resistance to increase. An optimum line width of 6 m results from this tradeoff.

All inductors were designed using the Ansoft HFSS software.7 The accuracy of this computer-aided-engineering (CAE) software at millimeter-wave frequencies has been repeatedly confirmed through previously fabricated inductor test structures in three different CMOS and SiGe BiCMOS technologies, with results obtained from three different foundries.7-9 Inductor 2-p models10,11 have proven helpful during simulation to include skin effects at high frequencies.

The RF pads were constructed by using a ground plane below the pads to isolate the silicon substrate from the pads. These pads can be modeled by means of a single capacitor. In the Q-band LNA design, these pad capacitors contributed in matching the input and output of the LNA to 50 Ω.12 As a rule of thumb, an extra 15% capacitance due to the edge effect is added to the total capacitance.13

The small signal equivalent circuit for a single common-source CMOS device modeled in 90 nm technology,14 used extensively used for this LNA, is shown in Fig. 1. The intrinsic and extrinsic parasitic circuit elements play a significant role in the performance of MOS transistors at such high frequencies. Other important device parameters, mandatory for design process selection, are fT, and fmax. Their dependence on the intrinsic and extrinsic elements is also shown in Fig. 1. For the sake of completeness, the methods used to calculate key device parameters and extract different important parasitic elements from their SPICE models will be included in this article.

The maximum device frequency for a bulk CMOS process can be calculated by means of Eq. 1:

fmax = fc/2{(Rg + Rs + Ri)d + gm(CMiller/ Cgin)>}0.5 (1)


fc = gm/2pCgin (2)

Once fmax has been calculated, the upper and lower boundaries for the MOS transistor's NFmin can be calculated by means of Eq. 3:

NFmin 1 + (f/fT)m(Rg + Rs)>0.5 (3)


fT = fc/Miller/Cgin)>0.5 (4)


Cgin = Cgsi + Coverlap + Cfringing (5) CMiller = Cgdi + Coverlap + Cfringing (6)


Cgsi, Cgdi = the equivalent capacitance induced by the source/drain field effect into the channel;

Coverlap = the equivalent capacitance given by the diffusion of the low-dopeddrain/ source (LDD) regions under the gate; and

Cfringing = the parasitic capacitance, which depends on the gate height and on the contact-to-gate distance.14

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As reported in the literature, the gate-source, gate-drain, and parasitic source/ drain bulk capacitance per unit gate width of p/n-MOSFETs remain constant across technology nodes at approximately 1 fF/ m, 0.5 fF/m, and 1.5 fF/m, respectively. 3,4 These standard values were also used as a basis in this work. Similarly, the gate resistance was calculated based on layout geometry, contact resistance, and salicided gate poly resistance data.

For SPICE modeling and simulation of the 90-nm process devices in the millimeter-wave frequency regime, the Berkeley SPICE BSIM4 (available for download from is this industry's model of choice. In this work, the extraction of important extrinsic parasitic elements for the above equations was done by using the BSIM4 intrinsic model shown in Fig. 2. As far as the noise performance is concerned, foundry compact noise models have been reported to fit measurements to 20 GHz. To capture noise effects at millimeter- wave frequencies, the BSIM4 noise partition model has been found to be a suitable choice for studying 90-nm silicon CMOS processes. The BSIM4 noise partition model is shown in Fig. 3.

With the above-mentioned dependencies of fT, fmax, and noise figure and the role of intrinsic noise-generating elements in mind, the layout of the transistors is of special importance in millimeter-wave circuit design. With a goal of minimizing noise figure and maintaining high gain at millimeter-wave frequencies, a two-stage, common-source LNA was designed (Fig. 4) with optimum input, output, and interstage matching networks. Those matching networks were created with lumped elements only, so as to achieve minimal noise levels.

In addition to its importance for a proper impedance match, substrate grounding was also critical for achieving high gain and low noise figure. The device technology used to fabricate the LNA is the L90 90-nm RF CMOS process from Infineon Technologies. Figure 4 shows a simplified schematic diagram of the LNA, excluding bias circuitry.

The first amplifier stage was sized and biased for minimum noise figure (NFmin), while the second stage was optimized for good gain and linearity. The input stage transistor was biased at 0.2 mA/ m and sized such that the real part of the optimum noise impedance provides a reasonable compromise between noise impedance matching (which requires a large device gate width), high gain and linearity (which requires large current), and insensitivity to impedance mismatches and process variations (which calls for low Rn and, thus, large current and gm). Transistors M1 and M2 feature 20 and 30 gate fingers, respectively. It was found that if the gate-source voltage, VGS, was fixed at 0.6 V, the corresponding transition frequency, fT, values were 84, 92, and 98 GHz, respectively, at drain-source voltages, VDS, equal to 0.5, 0.75, and 1 V. The values for the maximum frequency of oscillation, fmax, were found to be 72, 76, and 80 GHz, respectively, at VDS voltages of 0.8, 1.05, and 1.4 V.

The two-stage common-source LNA achieves maximum gain of more than 14.3 dB from 34 to 37 GHz with average gain of 12 dB over the broad bandwidth from 32 to 39 GHz (Fig. 5). The noise figure is a bit high over the lower range of frequencies, but is only about 3 dB for the bandwidth of interest (Fig. 6). Reflection coefficients S11 and S22 are at a minimum of -38 dB at 38 GHz (Fig. 7). As Fig. 8 shows, the LNA is unconditionally stable over a large swept power range, with no substantial second- or third-order nonlinearities. The LNA design achieves this performance with very low current consumption of 6 mA per stage from a 1.4-V supply. The table compares the performance of this millimeter-wave LNA with some previous work in millimeter-wave silicon-based LNAs.15-21

In summary, the Q-band LNA achieved reasonably good performance from a 90-nm silicon CMOS process. The design made use of high-density multimetal spiral inductors and nontraditional inductor structures, placed above metal ground planes and used in the amplifier's matching networks. These inductors enabled a maximum gain of greater than 14 dB from 34 to 37 GHz with an average gain of 12 dB from 32 to 39 GHz, and average noise figure of 3 dB. The S11 and S22 performance exceeded -35 dB at 38 GHz, with only 6.6 mA current consumption per stage from a 1.4-V supply, exceeding the best performance levels of the other silicon-based millimeter-wave amplifiers listed in the table.

1. Shao-Qiu Xiao, Ming-Tuo Zhou, and Yan Zhang, Millimeter Wave Technology in Wireless PAN, LAN, and MAN, Auerbach Publications, London, 2008.
2. A. K. Ezzeddine, "Advances in Microwave & Millimeter-wave Integrated Circuits," National Radio Science Conference, NRSC 2007, March 13-15, 2007, pp. 1-8.
3. Ali M. Niknejad and Hossein Hashemi, Hossein, Eds., mm-Wave Silicon Technology, 60 GHz and Beyond, Springer, Amsterdam, 2008.
4. N. Weste and D. Harris, CMOS VLSI Design. Boston, Addison-Wesley, 2005.
5. Duixian Liu, Ullrich Pfeiffer, Janusz Grzyb, and Brian Gaucher, Eds., Advanced Millimeter-wave Technologies Antennas, Packaging and Circuits, Wiley, New York, 2009.
6. F. Kuroki, F., R.-J. Tamaru, R.-T. Masumoto, Y.-S. Omote, "Bilaterally Metal-Loaded Tri-Plate Transmission Line (BIT Line) As a Low- Loss Printed Transmission Line at Millimeter-Wave Frequencies," IEEE China- Japan Joint Microwave Conference, September 2008, pp. 675-678.
7. HFSS software, Ansoft,
8. T. Dickson et al., "30-100 GHz Inductors and Transformers for Millimeter-Wave (Bi) CMOS Integrated Circuits," IEEE Transactions on Microwave Theory & Techniques, Vol. 53, No. 1, January 2005, pp. 123-133.
9. M. Gordon et al., "65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers," IEEE SiRF Digest, January 2006, pp. 265-268.
10. Sun Sheng, R. Kumar, S. C. Rustagi, K. Mouthaan, and T. K. S. Wong, "Wideband lumped element model for on-chip interconnects on lossy silicon substrate," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.
11. P. Russer, M. Righi, C. Eswarappa, and W. J. R. Hoefer, "Lumped element equivalent circuit parameter extraction of distributed microwave circuits via TLM simulation" IEEE MTT-S International Microwave Symposium Digest, 1994, pp. 887-890.
12. A. Aktas and M. Ismail, "Pad de-embedding in RF CMOS," IEEE Circuits and Devices Magazine, Vol. 17, No. 3, May 2001, pp. 811.
13. Yu Kyung-Wan and M. F. Chang, "CMOS K-band LNAs design counting both interconnect transmission line and RF pad parasitics" IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2004. IEEE Digest of Papers, pp. 101-104.
14. Thomas H. Lee, Planar Microwave Engineering: A Practical Guide to Theory, Measurement, and Circuits, Cambridge University Press, Cambridge, England, 2004.
15. Bo-Jr Huang, Huei Wang, and Kun-You Lin, "A Miniature Q-band CMOS LNA with Triple-cascode Topology," IEEE Microwave Symposium Digest, Boston, 2009 (MTT-S 2009), pp. 677-680.
16. Xu Leijun, Wang Zhigong, Li Qin, and Zhao Yan, "Design of a 40-GHz LNA in 0.13-m SiGe BiCMOS," Journal of Semiconductors, Vol. 30, No. 5, May 2009, pp. 0550-0514.
17. Mikko Varonen, Mikko Krkkinen, Mikko Kantanen, and Kari A. I. Halonen, "Millimeter-Wave Integrated Circuits in 65-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 43, No. 9, September 2008.
18. S. Montusclat, F. Gianesello, and D. Gloria, "Silicon full integrated LNA, filter and antenna system beyond 40 GHz for MMW wireless communication links in advanced CMOS technologies," in 2006 IEEE Radio Frequency Integrated Circuits Symposium Digest, San Francisco, CA, June 2006, pp. 9396.
19. H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, "Millimeter-Wave CMOS circuit design," IEEE Transactions on Microwave Theory & Techniques, February 2005, pp. 472477.
20. M. A. Masud, H. Zirath, M. Ferndahl, and H.-O.Vickes, "90-nm CMOS MMIC amplifier," in 2004 IEEE Radio Frequency Integrated Circuits Symposium Digest, Fort Worth, TX, June 2004, pp. 201204.
21. F. Ellinger, "2642 GHz SOI CMOS low noise amplifier," IEEE Journal of Solid-State Circuits, Vol. 39, No. 3, March 2004, pp. 522528.

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