Inductor-Less LNA Promises To Cut Noise

Aug. 12, 2011
TODAY'S WIRELESS industry requires the ongoing development of multiband/multi-standard terminals for low-cost and multifunction transceivers. The current trendusing single wideband front endsaccommodates all of the diverse wireless ...

TODAY'S WIRELESS industry requires the ongoing development of multiband/multi-standard terminals for low-cost and multifunction transceivers. The current trendusing single wideband front endsaccommodates all of the diverse wireless standards while reducing chip area. Yet these single front ends must consume little power, provide high linearity, and keep noise down, making the performance of their lownoise amplifiers (LNAs) key. An LNA that uses a composite NMOS/PMOS crosscoupled transistor pair to increase amplification while reducing the noise figure has been introduced by Ahmed A. Helmy, Edgar Snchez-Sinencio, and Kamran Entesari from Texas A&M University together with Vidatronic's Mohamed El-Nozahi.

This approach partially cancels the noise generated by the input transistors. The LNA's architecture is similar to that of a conventional broadband LNA with resistive matching. Yet it lowers the overall noise figure by connecting the gate of an input transistor to the gate of an output transistor in a cross-coupled fashion. This composite configuration reduces the output noise of both transistors. Input matching is adjusted through the feedback resistance and the LNA's overall effective transconductance.

The researchers implemented a prototype using 90-nm CMOS technology from IBM Corp. They then evaluated it using on-wafer probing and packaging. From 2 to 2300 MHz, the LNA offers conversion gain of 21 dB. It has an input third-order intercept point (IIP3) of -1.5 dBm at 100 MHz. From 100 MHz to 2.3 GHz, the LNA provides a noise figure of 1.3 dB minimum and 1.7 dB maximum. It consumes 18 mW from a +1.8-VDC supply. See "An Inductor-Less Noise-Canceling Broadband Low Noise Amplifier with Composite Transistor Pair in 90 nm CMOS Technology," IEEE Journal Of Solid-State Circuits, May 2011, p. 1111.

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