MIMO System Achieves 108-Mb/s Data Rate Using 16-MHz Channel

June 13, 2007
Higher data rates can be achieved by using wider RF bandwidths. Yet those bandwidths reduce the number of users that can simultaneously be connected to the network. A number of technologies have emerged to resolve this issue. Recently, a fully integrated ...

Higher data rates can be achieved by using wider RF bandwidths. Yet those bandwidths reduce the number of users that can simultaneously be connected to the network. A number of technologies have emerged to resolve this issue. Recently, a fully integrated 5-GHz, 2 X 2, multiple-input multiple-output (MIMO), wireless-local-area-network (WLAN) transceiver, RFintegrated-circuit (RF IC) was implemented in 90-nm CMOS. This RF IC was developed by Intel Corp.'s (Hillsboro, OR) Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Nati Dinur, Stewart S. Taylor, and K. Soumyanath.

MIMO technology uses multiple antennas and advanced digital-signal-processing (DSP) technology to exploit multipath effects. It can be used in two different modes. In this paper, the researchers focused on increasing the data rate through spatial multiplexing. Using two receive and two transmit antennas, the fabricated prototype can achieve a data rate of 108 Mb/s in a 16-MHz RF channel. The resulting spectral efficiency is double the efficiency of a legacy 1 X 1 system based on IEEE 802.11a/g technology.

To maximize MIMO phase noise without introducing undesired crosstalk, the engineers designed a shared local-oscillator (LO) generation and distribution network. In the presence of a 25-ns Rayleigh fading channel, the fabricated MIMO receiver achieves a sensitivity of –63 dBm while receiving 108 Mb/s in MIMO spatial multiplexing mode. The sensitivity of one receiver in the presence of AWGN noise is –76 dBm. See "A 5-GHz 108-Mb/s 2 X 2 MIMO Transceiver RF IC with Fully Integrated 20.5dBm P1dB Power Amplifiers in 90-nm CMOS," IEEE Journal of Solid-State Circuits, December 2006, p. 2746.

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