AS SYSTEM OPERATING frequency and projected die size increase, it has become more difficult to distribute clock signals across a chip. The resulting problems include larger R-C delays, tighter skew and jitter tolerance, and signal dispersion along metal interconnect paths. To reduce skew and the impact of dispersion, a compact, wireless clock distribution system with an external planar antenna has been proposed by Maxim´s Ran Li, Silicon Laboratories´ Xiaoling Guo, RF MicroDevices´ Dong-Jun Yang, and Kenneth K. O from the University of Florida.
This system has been shown to provide phase and amplitude distributions suitable for synchronizing circuits over a 35-mm diameter circular area at 3 GHz. The system comprises a transmitter and an off-chip antenna and multiple clock receivers with on-chip antennas distributed over an integrated circuit (IC) or multiple ICs. The transmitter, which was fabricated in a 130-nm CMOS process, generates a 17-GHz clock signal. See "Wireless Clock Distribution System Using an External Antenna," IEEE Journal of Solid-State Circuits, Oct. 2007, p. 2283.
