Zero-IF GFSK Demodulator Consumes Just 190 μW

By operating at zero intermediate frequency, this Gaussian frequency shift keying (GFSK) demodulator creates a simple and low power receiver architecture.

When used in low-power transceivers with Gaussian-frequency-shift-keying (GFSK) modulation, zero intermediate-frequency (IF) architectures remain robust in the face of quadrature imbalances. They also allow for a simple low-pass filter to reject adjacent channels. With these advantages, a low-power transceiver clearly calls for zero-IF GFSK demodulators as well. Because such demodulators typically require two power-hungry analog-to-digital converters (ADCs), however, this concept does not work for low-power applications. At Spain’s Institute of Microelectronics of Seville, an alternative GFSK demodulation scheme with phase rotation was proposed by Jens Masuch and Manuel Delgado-Restituto. Rather than requiring resistors, this approach combines the weighted outputs of current mirrors.

The demodulator is based on a phase-domain ADC (Ph-ADC). It directly quantizes the phase information of the received complex baseband signal. In addition, the Ph-ADC linearly combines the in-phase/quadrature (I/Q) aspects of the incoming signal. To detect the zero crossings and build a 4-b digital representation of the signal phase, the generated phase-shifted versions are fed to comparators.

The proposed solution employs a resistor-less scheme, which performs phase rotations in the current domain. In addition to reducing the amplitude error of the phase rotation, the demodulator permits an area-efficient implementation. With the Ph-ADC, the integrated GFSK demodulator houses a channel-filtering programmable-gain amplifier (PGA) and a symbol decision block while occupying just 0.14 mm2. The I and Q signals are first filtered and equalized with the two-stage PGA over a dynamic range of more than 50 dB. Because the subsequent Ph-ADC only evaluates phase information, the PGA simply implements coarse gain steps of 6 dB. To enable external gain control, the PGA stages’ output voltages are monitored by overflow detectors.

The demodulator consumes 190 μW from a 1-V supply. For a 1-Mb/s data rate and 0.5 modulation depth, it demands an EB/NO of 14.8 dB for a bit-error rate of 0.1% considering a flicker noise corner of 150 kHz. It boasts 74 dB dynamic range and can tolerate carrier-frequency offsets of ±170 kHz. This demodulator satisfies the requirements for the Bluetooth Low Energy (BLW) standard. See “A 190-μW zero-IF GFSK Demodulator with a 4-b Phase-Domain ADC,” IEEE Journal Of Solid-State Circuits, Nov. 2012, p. 2796.

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