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UHF CPUs Promise To Secure RFID Communications

To Attach to Merchandise Ranging from books to fresh foods, radio-frequency identification (RFID) tags need physical flexibility. RFID RF integrated circuits (RFICs) also must be produced at extremely low cost. In addition, they have to be able to provide secure communication. To meet these demands, a 13.56-MHz RF central-processing unit (CPU) with a flexible and a glass substrate was proposed by Hiroyuki Takashina and Yoshinari Yamashita from TDK Corp.'s Devices Development Center (Ichikawa, Chiba, Japan) and a host of individuals from the Semiconductor Energy Laboratory Company Ltd. (Kanagawa, Japan). Those individuals include Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, and Shunpei Yamazaki.

These RFIC tags house an 8-b CPU and an RF circuit with a 4-kB ROM and 512-B SRAM. They boast a software-programmed decryption function. The RF CPUs are fabricated using polysilicon thin-film-transistor (TFT) technology. Both tags communicate using 915-MHz ultra-high-frequency (UHF) RF signals. By employing a single DES and an anti-channel attack routine in firmware, they promise to provide secure communication. The RFIC tags occupy an area of 10.5 mm in width and 8.9 mm in height. The tag on the flexible substrate is 145-m thick with a weight of 262 mg. For its part, the RFIC tag on the glass substrate consumes 0.54 mW at a power-supply voltage of 1.5 V. It communicates with a maximum range of 43 cm at a power of -30 dBm.

For reader-to-tag communications, the researchers adopted amplitude-shift-keying (ASK) modulation with 90-percent modulation depth, pulsewidth modulation, and a data rate of 70.18 kb/s. For tag-to-reader communications, they relied on backscatter modulation with the two subcarrier frequencies of 280.7 and 140.35 kHz and a data rate of 140.35 kb/s. To ensure the generation of a steady clock signal, a digital control clock generator is used instead of an analog phase-locked loop (PLL). That clock generator comprises a regulator, ring oscillator, and clock and data recover circuit (CDR) with a master counter. It also includes a slave counter, reset controller, master divider, and slave divider. Because high accuracy is not required for the frequency, only simple analog circuits are needed for the clock generator. See "UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems," IEEE Journal of Solid-State Circuits, January 2008, p. 292.

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