Low-Noise Synthesizer Generates 60 GHz

HIGH-DATA-RATE COMMUNICATIONS AT millimeter-wave frequencies, per IEEE 802.15.3c requirements, will require extremely stable, low-noise signals. To provide those signals, Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, and Akira Matsuzawa constructed a 60-GHz quadrature phase-locked-loop (PLL) frequency synthesizer with wide tuning range and low phase noise. The Japanese researchers, who hail from the Tokyo Institute of Technology, Panasonic Corp., and Fujitsu Laboratories, designed the source by coupling a 20-GHz voltage-controlled oscillator (VCO) and PLL to a quadrature injection-locked oscillator (QILO) as a frequency tripler to produce the 60-GHz output signals.

The 20-GHz PLL uses tail-feedback to lower the phase noise of the PLL through modulation of the tail current; it provides a signal with phase noise better than −105 dBc/Hz and capable of a 17% tuning range. Both the 20-GHz PLL and the QILO were fabricated as separate chips using a 65-nm CMOS process. The measured results for the combination show phase noise of better than −95 dBc/Hz offset 1 MHz from the carrier. The signal source consumes 80 mW power from a +1.2-VDC supply. See "A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications," IEEE Journal of Solid-State Circuits, Vol. 46, No. 11, November 2011, p. 2635.

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