Properly Packaging RF Semiconductors

Although often overlooked, the package is an inseparable part of an RF/microwave semiconductor device, contributing to electrical performance and long-term reliability.

Electronic packaging usually serves to protect what lies within. For RF and microwave devices, however, an ideal package must provide a physical barrier while appearing electrically invisible. And with the trend for increasing levels of integration at higher frequencies (see Wireless Demands Focus Designers On Integration), packages must often take on the electrical characteristics of the circuits they safeguard, even through millimeter-wave frequencies.

Depending upon their circuits, highfrequency designers have a wide choice of package options, from simple SOT housings to elaborate chip-scale packages (CSPs). As with many design options, a choice in packaging must fulfill a set of requirements that includes electrical performance, cost, size, level of hermeticity, and shielding. Low-cost plastic or epoxy packages may provide a solution for some circuits, such as small-signal passive components, but more robust ceramic packages might be needed for a power transistor expected to deliver high output-power levels. In addition to routing signals to and from an integrated circuit (IC), packages must also provide compatibility with other components in a system and support testing.

The lowest-cost housings are based on thermoset epoxy. For RF and microwave devices, packages based on metal and ceramic materials are more common, especially where hermeticity is important. For less critical applications, plastic drop-in (leaded) or surface-mount (leadless) packages are increasingly used through microwave frequencies.

Single-function devices can often be supplied in small-outline-transistor (SOT) or small-out-line-IC (SOIC) plastic packages or surface-mount quadflat- no-lead (QFN) plastic packages with dimensions of just a few millimeters. Last year, Peregrine Semiconductor introduced a 2-b, 3-GHz digital step attenuator based on an advanced silicon CMOS process that fit into a 12-lead 3 x 3 mm QFN package (see figure).

In some cases, ceramic materials, such as low-temperature cofired ceramic (LTCC), can support compact designs due to the integration of passive circuit elements. By forming circuits and packages from multiple layers of LTCC, passive circuits such as filters can be built into the package.

For higher levels of packaging integration, multiple functions must be either fabricated on a single IC die and housed in a multipin package, or several die with multiple functions must be connected within a common housing. These approaches are known as system-on-a-chip (SoC) packaging and system-in-a-package (SiP) approaches. The SoC approach supports high levels of integration by combining RF, analog, and digital functions onto a single IC substrate and mounting the die into a multipin package. The SiP approach employs different IC die with bond-wire interconnections within the package. Each functional portion of a circuit, such as baseband and RF, can be optimized by means of a different process. Of course, it adds the expense of fabricating different die and of handling multiple die and providing additional bond-wire connections.

Flip-chip mounting is used in cases where even the small amount of inductance from bond wire interconnections cannot be tolerated. Ideal for ball-gridarray (BGA) housings, the approach typically costs more than methods using automated bond-wire assembly.

At high power levels, the thermal conductivity of the packaging material is critical. The thermal conductivities of package materials range from about 25 W/mK for alumina (aluminum oxide, Al2O3) to 1800 W/mK for diamond.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.