Scaling silicon CMOS transistors to smaller and smaller dimensions has made them serious competitors to traditional high-frequency transistors in many RF and microwave applications.^{1} Of course, creating accurate models of these shrinking devices is an important part of modern computer-aided-engineering (CAE) design practices, and linearity is a key issue in these models especially for RF/microwave circuits, not only in high-power designs but in lower-power components such as low-noise amplifiers (LNAs).^{2} There are a number of sources of distortion in a silicon CMOS transistor; among these are the transistor's transconductance, g_{m}, nonlinear capacitances (mainly the gate-source capacitance, C_{gs}, and the gate-drain capacitance, C_{gd}), and the output conductance, g_{ds}. Because of nonlinear behavior, these parameters vary with the applied voltage on the gate and the drain of the transistor. While many previous studies aimed at analyzing CMOS transistor nonlinearity,^{3-5} most of these studies looked at the distortion of the device as a whole using mathematical representations. As far as the authors are aware, no one has attempted physical level quantification of the sources of this distortion in the transistor model in the manner presented here.

Work undertaken in refs. 6 and 7 explained how table-based models can be built using symbolically defined devices (SDD) to represent each of the model's nonlinear parameters individually and independently from one another. Quantifying contribution to distortion form MOSFET's nonlinear elements was discussed as an application that demonstrates the need for such a model. This work builds on the work of ref. 6 by presenting the methods used to obtain linear representations of the nonlinear parameters in the transistor model. These linear representations of the model parameters are then used in the quantification process by switching the representation of the model's parameters between their linear and nonlinear representations, as will be demonstrated. Voltage-controlled charge sources are used to represent nonlinear capacitances for this work.

Linearizing nonlinear elements of a transistor model implies that the resulting model's characteristics are not a real representation of the modeled transistor but of an assumed transistor where the nonlinear parameters are made linear. The linearization mechanism should ensure that the fundamental response of the model should stay the same, and only its nonlinear behavior is affected. Discussion of the linearization process will be divided into linearizing the transconductance, linearizing the output conductance, and finally linearizing the nonlinear capacitances in the model

The transconductance, g_{m}, is essentially a voltage-controlled current source that describes the change in the small-signal drain current, i_{DS}, with respect to the small signal gateto- source voltage, V_{GS} . Therefore, when considering the linearization of the transconductance, two issues must be kept in mind. In order to correctly model g_{m}, linearly or nonlinearly, variance must be present. Therefore, replacing the SDD representing the transconductance current (I _{gm}) characteristics in ref. 6 with a current source at a single value (that of the respective operating bias point) or inserting the respective current value in the SDD as a single number are not valid methods of linearization, because no change is presented, and hence gm is not modeled correctly.

Also, it is well known that a voltage- controlled current source produces harmonics only if its current nonlinearly varies with its controlling voltage. If the current linearly varies with the controlling voltage, no harmonics are produced. The situation is different with nonlinear capacitances, as will be discussed.

In light of these two realities, and bearing in mind that the linearization should not affect the fundamental output of the transistor but only its nonlinear distortion, there are two options for linearizing the model's transconductance: Either by using a voltage-controlled current source Agilent Technologies> and setting its g_{m} to a value at the respective operating bias point, or by linearizing the values in the current characteristics data table.

The method of using a single-gm VCCS satisfies the variance condition in modeling the transconductance since g_{m} itself describes the change in I_{DS} with respect to V_{GS}. Also, since there is only one value of g_{m} at any input power, this change is linear. However, while a good S-parameter match can be obtained with this representation (since this value of g_{m} will be valid around close proximity of the bias point due to the very small signal used in the S-parameter test), the problem with this method is at high input power. When the input power significantly changes, the value of g_{m} set in the VCCS will no longer be valid and hence the fundamental output of the model is not expected to match that of the modeled transistor. This is because the total input voltage will expect to see another g_{m} value corresponding to the higher level input from the table that no longer exists. This problem is demonstrated in Fig. 1 where there is a good match between the fundamental output of the model and the transistor at low input power, but as the input power increases, the fundamental output of the model deviates further from the transistor's fundamental output.

Linearization by changing the data in the Igm table works by changing the current level in each V_{GS} curve, of the transistor's I_{DS} V_{DS} characteristics of Fig. 3, when the transistor is in saturation. This method overcomes the drawback of the VCCS method in that several characteristic curves at different levels will be presented, from which gm is to be extracted, hence gm no longer has a single value. The strategy is to use the original nonlinear I_{gm} data table to plot I_{gm} versus V_{GS} as shown in Fig. 2(e), choose a V_{GS} bias point and plot a tangent of the I_{gm} versus V_{GS} characteristics at this point. The new values for the DC current in saturation are then taken from the linear tangent line rather than from the nonlinear tablegenerated characteristic line. A new linear-g_{m} table is then established. Implementation of this linearization method was designed with full automation, adaptability and reusability in mind. Figure 2 details the data display window coding equations that were used to perform this procedure and its results.

In Fig. 2(a), VDSpoint is a variable used to select a value from simulated drain voltages where the Igm - VGS characteristics used for linearization is to be plotted. Generally, any point in the saturation area of the highest V_{GS} characteristic curve is valid. VDSindex=find_index (indepVDS,VDSpoint) finds the sweep index of the selected V_{DS} value. indepVDS is used to remove the dependency of V_{DS} on V_{GS} that is generated from the sweep setup, but is undesirable in the manipulation of the functions. Parameter midVGS is a variable used to store the value of the chosen V_{GS} bias point at which the linear tangent line will be drawn. Here, it is done in the middle of simulated VGS values to get as maximally valid linearization as possible at a wider range of bias points, but any other VGS value can still be selected. midVGSindex= find_ index(VGS,midVGS) finds the sweep index number of this point.

The equations in Fig. 2(b) find the slope of I_{gm} - V_{GS} characteristic curve at the chosen V_{GS} bias point, needed for drawing the linear tangent. IgmChange=TableIgm - TableIgm calculates the change in I_{gm}. The change is calculated between the selected bias point (specified by midVGSindex and VDSindex) and the next swept point on the VGS scale (specified by ), for extra accuracy. This setup ensures that this process is adaptable to any change in selected bias points. The change in V_{GS} is calculated similarly. The slope of the characteristic line is then evaluated in Slope=IgmChange/ VGSChange.

The equations in Fig. 2(c) plot the linear I_{gm} - V_{GS} characteristic line. The first four equations plot an initial linear line using the calculated slope, and make it overlap the characteristic line at the chosen bias point. LinearIgm= if (LinearLine<0) then 0 else LinearLine removes the negative part of the LinearLine and establishes 0 characteristics for Igm from the V_{GS} point at which the LinearLine crosses 0 I_{gm}, producing the linearized characteristic in Fig. 2(d).

The equations in Fig. 2(e) plot the linear I_{gm} - V_{DS} characteristic line. VDSSatPoint=VDS finds the V_{DS} value at which saturation occurs. SatPointIndex specifies the knee of each V_{GS} curve at which the transistor enters saturation. VDSSat=VDSSatPoint ensures that only one VGS curve (specified by VGSindex) is being handled every time. In LinearIgmVGS=if (VDS<VDSSat) then Ids else LinearIgm, the I_{gm} current level in each V_{GS} curve is modified to the new value taken from the linear tangent line after the saturation point (on the V_{DS} scale). This is done by searching all V_{DS} values if they were smaller or larger than the saturation point of that V_{GS} curve. If it is below, the value of LinearIgmVGS is taken from the original nonlinear current table (Ids), if it is on or after saturation, the value of Igm is given its value from the linearized I_{gm} - V_{GS} characteristic line in Fig. 2(d). Fig. 2(f) demonstrates the change of Igm current level in saturation on a single VGS curve. With this value of V_{GS}, the transistor saturates at V_{DS} of 2.3 V. From this point forward, the current is replaced by its new value and the V_{DS} curve is modified. Figure 3 demonstrates how the I_{gm} - V_{DS} characteristics change using a number of V_{GS} curves. These new V_{GS} curves form the new linearized Igm data table that is used for quantification. Note that the actual work was performed on many more V_{GS} curves with 0.05-V steps in the range from 0 to 3 V.

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Figure 4 demonstrates the need for having the process explained above automated. This is a zoom of an I_{gm} - V_{DS} characteristics similar to that of Fig. 3 but produced when fewer V_{GS} curves are used (in steps of 0.25 V). Thorough observation of the curves in Fig. 4 reveals a serious problem. According to the linearization method, the current level of each V_{GS} curve is to be changed from its saturation point forward, but only once. However, observing Fig. 4 reveals that this is not the case. Taking the curve of V_{GS} = 2.9 V as an example, the current level first changes when the transistor saturates at VDS = 2.35 V, but then it changes again at V_{DS} = 2.6 V which is the same point at which the upper curve (V_{GS} = 3 V) saturates and changes. The lower curves (V_{GS} = 2.8, 2.7 and 2.6 V) follow the same theme, each with all the curves above it. But this does not happen to the V_{GS} curve at V_{GS} = 2.5 V. This phenomenon is due to interpolation. Since the simulated step is 0.25 V, the curves at V_{GS} = 2.5, 2.75 and 3.0 V have their data available in the table, what is between them is interpolated, and the observed error is due to how the interpolation works. The straightforward solution to minimize this error is to use many more data points. This can be very time consuming and may lead to errors, hence automation is needed. As demonstrated, the coded functions above take care at every step of retaining the dependency on the swept values of V_{GS} and V_{DS} in linearizing the Igm current, making the procedure accurately adaptable on any device and easily applicable by the designer for any accuracy required.

For most accurate results, the produced model with the linear Igm should be biased at the same point at which the linear tangent line was drawn. With this, an S-parameter simulation produces a good fit to the original transistor. Again, this is because the S-parameters' test signal is very small and hence will not change the operating point from that at which the linear tangent line was drawn. However, when a large input signal spread over the linear line is applied, the fundamental is expected to be different because the linear line does not represent the original characteristics. Nevertheless, tests showed that this error is very inconsiderable. This can be related to the fact that the difference between the linear line and the original characteristics is insignificant as shown in Fig. 2(d). But, as will be seen in the next section this linearization has an important effect on the thirdorder intermodulation distortion (IMD3) components of the model. The output conductance g_{ds} is linearized by changing its representation to a voltage-controlled resistor as in ref. 7 and using the corresponding value of gds is extracted at that bias point.

Unlike VCCS, a voltagecontrolled capacitance produces harmonics just as it is variant with its controlling voltage, linearly or nonlinearly. In light of this, in order to linearize a nonlinear capacitor, it has to have a single value at any applied external voltage. For the purpose of quantification in this work, this can be achieved in two ways. The first approach involves replacing the SDD representing the nonlinear capacitance with a single value capacitor from the component library. This is an easy and straightforward option, but it lacks the benefits of representing capacitance as charge sources. As a second approach, if the capacitance is to be represented as a charge, nonvariance can be achieved by changing the SDD's table, copying the charge value at the operating bias point to all other values of V_{GS} and V_{DS} in the table. The first option was adopted here due to its simplicity and straightforwardness.

REVIEWING RESULTS

The bias point and the range of input powers used in quantifying the nonlinear distortion from the transistor's nonlinear elements are crucial to the validity of the quantification process and its results. Broadly, it is recommended that very high input powers should not be used, and that is due to three reasons. First, it is important that the transistor operates in the area where the I_{gm} - I_{gds} separation discussed in ref. 6 is valid, i.e., the input power signal swing should not take the operation of the transistor to the linear region. The choice of the bias point also helps avoiding this by biasing the model far from the linear region. Also, the operation of the transistor needs to be confined to the area where the interpolation error of the linearized Igm discussed earlier does not come into effect. This can lead to inaccuracy and introduce errors. Finally, very high input powers will make the single values used for linearizing the output conductance and capacitances no longer valid, as it will push the transistor far from it bias point and can corrupt the result. The input power should also not be very small since that makes the effect of interpolation (present in any data table as required by harmonic balance simulation) more significant. Bearing these points in mind, and following some experiments on the linearized model, the choice was made to carry the quantification process at moderate input power levels of -25 to -5 dBm.

In Fig. 5, some quantification results are presented to demonstrate the validity of the idea of quantifying the contribution to distortion from nonlinear elements through nonlinear modeling. An S-parameter test was done every time to verify the small signal operation of the modified model with different parameters linearized.

In Fig. 5(a), all elements are nonlinear. Parameters g_{m} and g_{ds} are represented by their nonlinear data tables, while capacitances C_{gs} and C_{gd} are represented by their charge source tables. As expected, almost identical IMD3 product over the simulated input power range is produced from the transistor and the model. In Fig. 5(b), parameters g_{m} and g_{ds} are nonlinear while capacitances C_{gs} and C_{gd} are linear. There is almost no difference between the IMD3 product of the transistor and the model indicating that the contribution from these capacitances to the nonlinear distortion is minimal. Therefore, in the tests of Fig. 5(c) through Fig. 5(e), the representation of the capacitances is left linear to study the effect of a linear or nonlinear gm and gds on the total IMD3 distortion. In Fig. 5(c), with g_{m} linearized and g_{ds} nonlinear, a reduction in IMD3 of about 15 dB can be observed. In Fig. 5(d), both gm and g_{ds} are linearized. Now the reduction in IMD3 is much greater than in Fig. 5(c) with a maximum of -45 dBm. However, in Fig. 5(e), with g_{m} nonlinear and gds linear, no reduction in IMD3 is observed. The results in Figs. 5(c) and 5(d) in comparison with Fig. 5(e) presents an interesting observation. While the contribution of nonlinearity is obvious when comparing Figs. 5(c) and 5(d), Fig. 5(e) suggests that this contribution is only significant when g_{m} is linear. When g_{m} is nonlinear, it dominates and the effect of a linear g_{ds} on reducing IMD3 is insignificant. A similar observation can be made from the result in Fig. 5(f) where all nonlinear elements are set as they were for the test in Fig. 5(d) except C_{gd}, which is nonlinear using its voltage-controlled charge sources table. Notice that while Fig. 5(b) shows no reduction in IMD3 as a result of linearizing Cgd, comparing the results in Figs. 5(f) and 5(d) reveals that a notable increase in IMD3 resulted from making C_{gd} nonlinear.

This unique and fully automated method effectively linearizes the transconductance of a silicon CMOS transistor from its table-based model. Linearized representations were used to quantify contributions to distortion from the model's nonlinear elements. The quantification results revealed the validity of the process through transistor nonlinear modeling where each nonlinear element is independently represented. They also verified the effectiveness of the linearization techniques proposed. These results also show that there is a strong correlation between the nonlinearities in the transistor. This raises the necessity for improving this method by maintaining separate representations of each nonlinear element while accounting for the correlation between these nonlinearities.

REFERENCES

1. Wei Guo et al., "The Noise and Linearity Optimization for A 1.9-GHz CMOS Low Noise Amplifier," Proceedings of the IEEE Asia-Pacific Conference on ASICs, pp. 253-257.

2. Tae Wook Kim et al., "A Low-Power Highly Linear Cascoded Multiple-Gated Transistor CMOS RF Amplifier with 10 dB IP3 Improvement (Revised)," Microwave and Wireless Components Letters Vol. 13, 2003, pp. 420422.

3. Piljae Park et al., "Linearity, Noise Optimization for Two Stage RF CMOS LNA" Proceedings of IEEE TENCON International Conference on Electrical and Electronic Technology, Vol. 2, 2001, pp. 756758.

4. Ickjin Kwonl et al., "An Integrated Low Power Highly Linear 2.4- GHz CMOS Receiver Front-End Based on Current Amplification and Mixing," IEEE Microwave and Wireless Components Letters, Vol. 15, 2005, pp. 3638.

5. Vladimir Aparin et al., "Linearization of CMOS LNA's Via Optimum Gate Biasing," Proceedings of the International Symposium on Circuits and Systems, Vol. 4, 2004, pp. 748-751.

6. A. M. T. Abuelmaatti and I. and Thayne, "A New RF Si CMOS SDD Model for Quantifying Individual Contribution to Distortion from Transistor's Nonlinear Parameters," Proceedings of IEEE International Conference on Electronics, Circuits and Systems, Paris, France, December 2006.

7. A. M. T. Abuelmaatti, I. Thayne, I. McGregor, and E. Wasige, "A New Implementation for RF SiCMOS Transistor Model Using SDD for Quantifying Individual Contribution to Distortion from Transistor's Nonlinear Parameters," in the Proceedings of the Asia-Pacific Microwave Conference, Tokyo, Japan, December 2006.