Developing Designs For RFID Transponder Using DTMOS

where:
F = F_BJT = V_BE
for a bipolar transistor and
F = F_WIM = GS– V_T).C_OX/(C_OX + C_depletion)>
for a weak-inversion MOS transistor.
The value of the depletion capacitance depends on the width of the depletion layer, which in turn depends on the well doping characteristics and the voltage drop in the silicon near the source junction. Hence, the factor depends on the applied well-source voltage and on the applied well-source voltage via the threshold modulation effect.

DTMOS can be viewed as a lateral bipolar PNP with an extra gate over the base. Based on this view, DTMOS’s drain current is primarily determined by the voltage across the source-well junction, which results in an ideal exponential (bipolar-like) relation between V_GS and I_D. Due to the presence of the interconnected gate-well, there is a built-in voltage F_GW between the gate and well. Voltage F_GW is subdivided over the gate oxide and over the silicon due to capacitive division. Denoting the voltage drop in the silicon due to F_GW as the barrier lowering voltage F_b1, it can be shown that the drain current of a DTMOS is:

The barrier lowering voltage Fb1 is given by:

which is a function of FGW and of a number of process parameters. Derivations from refs. 1-4 show that:

The key results from these derivations are as follows:
• The apparent bandgap of a DTMOS device is 0.6 V compared to 1.2 V for a silicon PN junction.
• The DTMOS device follows an ideal exponential characteristic D a exp(qV_GS/kT)>
• The DTMOS device’s lateral current is a factor of exp(qFb1/kT), which is larger than ordinary lateral PNP counterpart.
• The apparent bandgap voltage is temperature dependent.

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An initial, successful design fabricated with quarter-micron DTMOS technology operated at 77 K using a supply voltage of 0.6 V with the body substrate tied to the fixed forward bias.⁵ Later experiments involved gate controlled lateral bipolar transistor (GCLPNP)⁶ and silicon-on-insulator (SOI) MOSFET⁷ technology with the substrate tied to the gate terminal. The first technology is used for a miniature lowpower analog application while the second is typically the best candidate for ultralow-power CMOS.

DTMOS technology shows an impressive figure of merit in its gate-delay/power-consumption product compared to conventional CMOS. DTMOS also shows superior performance in RF circuits. In conventional CMOS, technology scaling to smaller feature sizes and threshold voltages (V_TH) increases the operating speed. However, lowering V_TH also leads to degraded subthreshold MOSFET behavior. The standby current increases in static circuits, thus limiting V_TH to 0.4 V. DTMOS can possibly overcome such constraints, especially operation at very low V_DD and low V_TH with steep subthreshold characteristics. With DTMOS, the gate input voltage forward biases the substrate, hence V_TH will decrease according to the well-known body effect equation⁸:

Based on this equation, DTMOS can achieve low V_TH in its "on" state. At the same time, in its "off" state, it maintains a steep subthreshold slope similar to that of non-scaled conventional MOSFETs to minimize reverse leakage current. This is accomplished by varying the V_BS component in the body effect equation in the DTMOS "on" and "off" states.

Several groups have demonstrated various physical implementations of bulk-DTMOS (B-DTMOS) for digital circuits. In early work, two groups created B-DTMOS logic circuitry by tying the CMOS gate and well together.^9,10

This approach has the advantage of efficient use of substrate real estate. Still, results from both research groups exhibited limited V_DD, in the range of 0.6 to 0.8 V. Seizo Kakimoto and his research team made some improvement on this V_DD limitation.¹¹ Their work involved the use of a self-adaptive power-supply scheme (Fig. 2) to generate the necessary voltage supply, so that their BDTMOS achieved enhanced stability compared to earlier work, at the expense of additional control circuitry and larger chip size.

Another approach was revealed at the 1996 IEDM: an ultra-low-power logic circuit using modified advanced isolation (SITOS) CMOS with gate-to-shallow-well contacts (SSS-C) to achieve BDTMOS. By using a modified CMOS process, the parasitic well capacitance was minimized and a higher operating frequency was achieved.¹²

Besides using B-DTMOS in a simple static CMOS logic configuration, other logic schemes based on DTMOS were proposed by Elgharbawy in the form of domino B-DTMOS (B-DTPMOS) logic, which route the clock signal to the substrate.¹³ Connecting the system clock in dynamic circuits to the common substrate of all the NMOS transistors improves the switching speed and the driving capability of the domino-like circuits at the cost of a slight increase in power consumption compared to conventional subthreshold domino schemes. Furthermore, B-DTPMOS can be combined with the B-DTNMOS for even faster operation and higher driving capability with a slight increase in power consumption. Still, it yields a 43.2-percent energy savings compared to the conventional subthreshold domino scheme. These results indicate that the proposed RFID transponder scheme is well suited for battery-powered devices, where energy conservation is a primary concern.

Most of the early work on DTMOS has focused on digital circuitry, due to the low power capability of the technology. But recently, two groups demonstrated promise for DTMOS in analog applications. One group achieved a low-voltage (1-V) operational amplifier (opamp) with 35.7-MHz unity-gain frequency and 64-deg. phase margin under load conditions of 5 pF and 10 kΩ.¹⁴

The other group fabricated a stable bandgap reference circuit using dynamic-threshold MOS transistors.¹⁵ Suitable for low-voltage, low-power ICs which can tolerate moderate accuracy, the bandgap-reference circuit runs on supply voltages as low a 0.85 V and generates reference voltage of 0.65 V while consuming only 1 µW power. The die occupies only 0.063 mm² area using a standard 0.35-µm CMOS process.

Apart from digital and analog applications, researchers from Taiwan National Chiao-Tung University pointed out the potential of DTMOS in RF applications as well.¹⁶ They implemented and studied a high-speed DTMOS structure using a standard 0.18µm CMOS process with deep N-well isolation from TSMC (Fig. 3). The DTMOS structure was found to exhibit a resistive nature at its input port because of the tied body gate; the forward bias V_BS was found to enhance the current gain and hence improve the frequency response.

In one experiment, the group reported that under low drain current, DTMOS exhibits enhanced cutoff frequency (f_t) and maximum frequency oscillator (f_max) performance. For example, they observed f_t of 65 GHz and f_max of 52 GHz for a drain current of 12.5 mA. The source-body capacitance extends the bandwidth but flattens the power gain. The input third-order-intercept-point (IIIP3) performance is also better for DTMOS than for conventional CMOS by 3.3 dB. The better linearity at low drain current suggests that DTMOS is an attractive process for RF amplifiers, although the output power is lower than conventional CMOS because of substrate losses due to the source-body capacitance.

DTMOS is a strong candidate for driver circuitry compared to CMOS, with its better transconductance-to-drain-source-current (g_m-to-I_DS) ratio at low current levels, indicating low channel resistance for DTMOS. Due to contribution of the parallel parasitic bipolar transistor, DTMOS exhibits excellent potential for driver circuitry. A positive feature of DTMOS is that its inherent body-to-source diode serves as electrostatic-discharge (ESD) protection, eliminating the need for additional ESD circuitry.

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Based on the results presented above, the current authors feel that DTMOS is an excellent candidate for a UHF RFID transponder rectifying device, as an alternative to Schottky contacts. The lowpower performance of DTMOS will also help to cut the power consumption of the RFID digital block.

The authors' group at Multimedia University, in collaboration with Silterra (Malaysia), has been involved in the development of a DTMOS UHF RFID transponder IC. One of the first projects involved the successful design, fabrication, and test of a bandgap-reference (BGR) circuit, employing the Silterra fabrication technology. A stable voltage reference is a vital component as part of the on-chip supply for an RFID transponder IC. It generates the drain voltage (V_DD) and is part of the stable power rail for the transponder's digital circuits and an on-chip oscillator. A well-designed reference source must remain stable with process variations, voltage, and temperature, without making adjustments in the fabrication process.

Conventional BGRs using CMOS technology typically employ diode-connected parasitic substrate vertical PNP transistors or lateral PNP transistors as diode elements. Typical bandgap designs require at least several tens of microwatts of power and provide a default output voltage of around 1.25 V, which is nearly the same as the bandgap voltage of silicon, extrapolated to 0 K .¹⁷

The V_DD supply voltage achievable in a UHF RFID IC is at the range of 1 to 1.5 V only for optimum range devices.¹⁸ A goal for a regulated V_DD RFID digital core supply is less than 1 V. Therefore, a conventional BGR is not suitable for RFID applications for two reasons: its high power consumption and relatively high reference voltage, and the minimum supply voltage (V_DD) required for the BGR. The solution proposed by the authors is shown in Fig. 4, a DTMOS BGR.

For the back-end of the device design, common layout techniques such as common centroid layout and dummy transistor techniques were employed to ensure device matching. High-resistance polysilicon resistors were used since they provide the best resistivity (Ω/square) among the resistor options available in the process, with a goal of minimizing the chip area. Simulation results were based on Silterra foundry HSPICE models. Due to the nature of DTMOS, there is the potential of the drain bulk junction being forward biased. Usually, SPICE (HSPICE) models fail to accurately predict device behavior for this scenario.

Figure 5 shows a micrograph of the DTMOS BGR. All measurements were performed on a wafer-probe station using an HP4156B parameter analyzer from Agilent Technologies (www.agilent.com). The measurements were generally in agreement with the simulations, as the table reveals.

The main contribution of B-DTMOS will be for the fabrication of a series of standard digital cells for the digital modules of UHF RFID transponders. B-DTMOS offers excellent digital performance under ultra-low-voltage conditions. Its lower leakage currents and higher speed compared to conventional CMOS circuitry imply great promise for future designs, although it is expected that the new digital cells will consumer larger chip areas than CMOS due to the additional complexity of the control circuitry.

In addition, DTMOS shows great promise for RF applications. Several researchers have explored the potential of the process for rectification, as an alternative to Schottky contacts. This would support low-cost production in a standard CMOS process compared to the post-processing efforts needed to fabricate Schottky contacts. Work continues with Silterra (Malaysia) to design a UHF RFID transponder IC using DTMOS on a standard, low-cost 0.18µm CMOS process, at present using a DTMOS structure in the design of the modulator and demodulator.

ACKNOWLEDGEMENT
This work was supported by Silterra Malaysia under its Malaysia University Multi Project Wafer (MPW) program. We also wish to thank Emerald Systems Sdn. Bhd. for providing the support to use the Mentor Graphics Tools.

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