Wireless SoCs Use Cortex-M0 Core To Slash Power Consumption

For more than a decade, designers of wireless products have been struggling to deliver ever-increasing performance while consuming less power. Among the latest products promising to satisfy these opposing demands are two wireless system-on-a-chip (SoC) devices from Nordic Semiconductor (www.nordicsemi.com). Conveniently, the first two low-power wireless SoCs in the nRF51 series share the same architecture and multi-protocol radio. While the nRF51822 has a Bluetooth-low-energy/proprietary 2.4-GHz stack, the nRF51422 has an ANT/ANT+ stack (see p. 42 for more on ANT).

This third generation of Nordic’s wireless integrated circuits (ICs) features a new, power-efficient architecture (see photo below). Compared to the company’s previous product generation, Nordic claims that both devices enable power reductions to 50% as well as RF link budget improvements of as much as 9.5 dB. These improvements are derived from the use of a new multi-protocol radio alongside a 32-b ARM
Cortex-M0 core.

“This project was codenamed Princess,” says Thomas Embla Bonnerud, Nordic’s Director of Product Management. “We had very ambitious goals. We wanted to do Bluetooth low-energy and ANT single-chip SoCs that had the ease-of-use of two-chip solutions.”

Perhaps most impressive of the nRF51’s qualities is its extremely low power consumption. Nordic made small enhancements to the radio’s current budget. But the biggest improvement came from a new power-management scheme. “Power modes 0, 1, 2, 3…We threw that away,” Bonnerud explains. “These devices are not constrained by power modes. Simply power-on in software [the blocks] you want and everything else remains asleep.”

Alongside the new power-management scheme is a programmable peripheral interface (PPI), which minimizes the central processing unit’s (CPU’s) active time to save power. Peripherals can therefore operate autonomously and talk to each other without waking the CPU. This approach also reduces real-time requirements on the CPU.

Introducing the ARM Cortex-M0 core to this IC generation improved processing speed by a factor of 10. Startup time has been reduced by a factor of 100 to 2.5 μs, which helps to save power. The company also managed to reduce the devices’ supply voltage from 1.9 to 1.75 V in order to “squeeze the last juice out of a coin cell or AA,” explains Bonnerud.

The devices’ multi-protocol radio also was entirely redesigned. It now incorporates EasyDMA (which stands for “direct memory access”). Essentially, it can access data directly from the memory, convert it to packets, and transmit it. An increased output-power range now stretches from −20 to +4 dBm. The radio’s sensitivity depends on its operational mode: For example, it is −92.5 dBm in Bluetooth low-energy mode. The 9.5-dB improvement in link budget is derived from a combination of these two specifications.

In terms of software, the nRF51 clearly separates its application and Nordic-provided stack code. Comparing this IC to older solutions, which had a single framework, the application and stack are now compiled separately. Dependencies between them have been removed. As a result, bugs in the application code will not affect the stack or vice versa.

According to Suke Jawanda, Chief Marketing Officer for the Bluetooth SIG (www.bluetooth.org), reducing power consumption by 50% could extend the battery life of some consumer devices up to eight years. The battery life would therefore exceed the lifetime of the device—an important milestone. From the SIG’s point of view, Jawanda adds, a chip that can do proprietary 2.4-GHz protocols and Bluetooth low-energy would definitely help ease companies’ transition to Bluetooth low energy.

Rod Morris, Vice President of ANT Wireless, emphasizes that the launch of the nRF51422—the world’s first ANT SoC—is a significant milestone. The IC’s 60-kb/s burst rate makes it three times faster than previous generations. ANT requires less than 32 kB of code space and 2 kB of random-access memory (RAM), leaving more than 224 kB of Flash and 14 kB of RAM for the application code. Morris points out that the single-chip solution also will contribute to making ANT-compliant devices smaller. The 32-b M0 core has been implemented in around 12,000 silicon gates. In other words, it fits into the same physical space that was formerly occupied by 8-b devices.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.