ISP Technology Draper
An advanced processor chip has been developed with built-in security features that provide self-protection when used in many different applications.

DARPA Designates Draper to Boost DoD Security

An advanced processor chip has been developed with built-in security features that provide self-protection when used in many different applications.

Electronic security is a critical and difficult-to-establish segment of any defense electronic system, and a function for which DARPA now looks to Draper for assistance. That help will come in the form of Draper’s System Security Through Hardware and Firmware (SSTH) program and a contract worth as much as $9.8 million. The contract provides the resources to develop hardware design tools with built-in cybersecurity and computing capabilities to counter software vulnerabilities in both military and commercial electronic systems. Draper’s cybersecurity technology has proven itself an effective information protection solution. It leverages the commercial processing ecosystem to provide information protection even under warfare applications.

Draper has developed a cyber-resilient embedded processor chip known as the Inherently Secure Processor (ISP), which makes it possible to focus on hardware security at the microarchitecture level. Although the device was nominally developed for commercial use, Draper hopes to show through the contract that it can be used to develop architectures and design tools that provide cybersecurity both for Department of Defense (DoD) and commercial applications.

“Draper’s cybersecurity capabilities and Inherently Secure Processor enable us to provide silicon chip developers and manufacturers with a design that embeds security directly into hardware at the processor level,” said Paul Rosenstrach, the company’s principal director of special programs. “ISP hardware enforces customizable software-defined security rules, enabling system designers to develop individual policies that fit their application.”

The ISP can be implemented with any reduced-instruction-set-computer (RISC) processor (see photo), and is currently optimized for the RISC-V architecture to operate as a co-processor with a system’s main processor or processors. The ISP approach features adaptable and updatable technology that arms customers with a flexible, long-term security solution.

  

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