Bluetooth has evolved from a low-throughput-rate (723 kb/s) short-range wireless link at 2.40 to 2.4835 GHz transmitting simple frequencyhopped, Gaussian frequency-shiftkeying (FSK) modulated signal. This early version of the unlicensed wireless standard (Bluetooth 1.2) shifts carriers by 160 kHz to represent the data bit, using frequency hopping at 1600 times/second onto one of 79 channels, each spaced 1 MHz apart. Newer versions of Bluetooth employ more complex modulation to increase the throughput rate. As a result, compatibility with the different Bluetooth formats requires a radio with a flexible intermediate-frequency (IF) section for the different spectral masks.
In the Enhanced Data Rate version of Bluetooth ("Bluetooth 2+EDR), for example, the throughput rate available for the payload packets is 2 Mb/s for mandatory differential quadraturephase- shift-keying (QPSK) modulation and 3 Mb/s for an optional differential 8PSK modulated signal. To maintain backward compatibility, both the access code, which is used by a receiving device to recognize an incoming transmission, and the header packets, which are used to describe the packet type and length, still use Gaussian FSK modulation. The higher-throughput rates available in the payload packets are useful mainly to establish a variety of links simultaneously.
In order to minimize any interference with other wireless links operating in the 2.4-GHz band, it is desirable to have a heterodyne receiver incorporating an analog IF filter with high performance. This architecture will not only avoid the issues of DC offset, in-phase and quadrature (I and Q) signal imbalance, 1/f noise contamination, and voltage-controlled-oscillator (VCO) pulling, it also relieves the dynamic range and sampling rate requirements for the analog-to-digital converters (ADCs) and simplifies the subsequent digital filtering requirements. The filtering can be done with an external surfaceacoustic- wave (SAW) RF filter. However, since a SAW filter cannot be integrated with other RF components into an RF integrated circuit (RFIC), it remains unattractive from a cost, size, and interconnection point of view.
Depending upon the current Bluetooth center frequency and surrounding interference environment, it may be advantageous to select a particular IF for the heterodyne receiver architecture. In addition, depending on the (slight) variations in spectral masks between Bluetooth 1.2 and Bluetooth 2+ EDR, it may be desirable to adjust the passband ripple and bandwidth. It may also be desirable to increase the suppression of adjacent-channel interference in highly congested radio environments. A single filter capable of supporting the triple-tuning requirements of multiple Bluetooth formats, and can be integrated into an RFIC transceiver, could help redefine the Bluetooth architecture.
Figure 1 shows a simplified version of a new on-chip reconfigurable IF filter. It is comprised of four major elements: a current replicator that generates multiple tap currents, each proportional to an input signal through constants TC0, TC1, and TC2; a "current rotator" that sends the tap currents to multiple integrators; multiple integrators, where the number of integrators is one more than the number of tap currents; and an output sampling and resetting circuit.
The tap current coefficients determine the filter response:
z = ej2nTi;
k = 1, 2,Nt 1; and
TCk = the tap coefficients.
The current rotator that is connected to the tap currents consists of a switch matrix, which is an array of switches coupled between any of the tap currents and any of the following integrators. Each of the integrators, CI, CI, CI, and CI consists of an operational amplifier and a capacitor. Finally, the output sampling and resetting circuit, which selects the correct integrator output at the correct sampling time, consists of output select switches, Ss1, Ss2, Ss3, etc.
Each of the integrators in the sampling RF filter periodically goes through two operating phases: an integrating phase during which there is at least one current being received, and a rest phase, when no tap current is received. During the rest phase, the integrator's charge is sampled by observing the voltage at its output. This is done by closing the corresponding output sampling switch, connecting the integrator to the subsequent circuits. The voltage on the integrating circuit output is then reset using the reset switch.
Figure 2 shows the timing diagram of the state changes of the four clock buses used in the current rotator of the filter shown in Fig. 1. Here, for example, when CK is high, the current from TC0 is integrated onto CI, then during the time when CK is high, TC1 is integrated onto CI
As an example, the response of a bandpass filter with 140-MHz center frequency and 256 tap currents is shown in Fig. 3 over a wide frequency range and in Fig. 4 around the passband. As expected for a sampling filter, undesired passbands exist on both sides of the sampling frequency. Since the sampling frequency being used by the filter is high (1.61 GHz), these unwanted passbands are far from the desired passband (140 MHz). Furthermore, these unwanted passbands are attenuated by the inherent sinc function operation of the integrating sampler. As Fig. 4 shows, the 3-dB bandwidth of 10 MHz features excellent passband ripple of better than 0.5 dB and adjacent-band attenuation of more than 64 dB.
Since the bandpass filter is an analog equivalent to a digital FIR filter, the center frequency can be changed by changing the sampling frequency that drives the current rotator. Also, the bandpass ripple and bandwidth can be adjusted by changing the tap coefficients. The depth of the adjacentchannel rejection can be increased by powering (enabling) more of the available number of tap currents. This feature enables a trade off to be realized between a high-performance, robust mode of operation and a low-power, modest blocker-rejection mode.