S-Band Power Amp Incorporates Bare Die

The use of unpackaged transistors and some clever circuit matching and signal-processing techniques help to shrink the size and cut the cost of a 100-W amplifier developed for pulsed S-band radar applications.

Radar systems require higherpower but affordable solidstate high-power amplifiers (HPAs). The design of an efficient, low-cost HPA is particularly challenging given the expense of high-frequency, packaged transistor devices. By eliminating the packages, however, it is possible to save on the cost of developing an HPA. By mounting bare silicon transistor die on aluminum-nitride (AlN) carriers, and protecting the devices with a low-cost plastic cover, an S-band HPA was assembled that provides the performance of designs based on packaged transistors, but at a fraction of the cost.

Several factors were considered in the design of the S-band HPA. 1 The first approach is to use the highest power-density transistors available to achieve the highest output power possible from a given size amplifier. The use of the latest transistor technology, be it silicon LDMOS, silicon carbide (SiC), or gallium-nitride (GaN), tends to be expensive. The second approach is the rely on (lower-cost) current transistor technology and design the amplifier in such a way to reduce both its size and cost while maintaining high output power.

The second approach was applied to the design of a 100 W S-band radar HPA.

The HPA was designed with a three-stage cascaded configuration (Fig. 1). Low-cost silicon-bipolar transistor die (Class C bias) were used for each stage, with a performance goal for the HPA of 100 W typical output power for 0.6 W input power for 300-µs pulses at 10-percent duty cycle in a 400-MHz bandwidth at S-band. Rather than a single transistor, the final (output) stage consists of two transistors combined with a Wilkinson divider/combiner. The topology provides high isolation between stages for high reliability. To keep the HPA compact (75 × 23 mm), inter-stage isolators were not used.

Silicon bipolar power transistors are often supplied mounted in ceramic or plastic packages for mechanical and environmental protection and to aid thermal dissipation. A ceramic package is usually soldered onto a copper-tungsten (CuW) baseplate. By mounting transistor die on an AlN carriers, good mechanical integrity is possible. The carriers have the same thickness as the amplifier's Duroid substrate, both of which are mounted on an aluminum baseplate for good thermal dissipation (Fig. 2).

The carriers contain both input and output impedance-matching networks. Nontoxic AlN material supports excellent thermal dissipation for the high-power pulsed transistors while providing the required electrical isolation between the baseplate (ground plane) and the bipolar transistor die in their common-base configuration. This topology results in the best possible integration with the transistor die having collector connections on the bottom.

Although different transistor die are used in the first and second amplifier stages, a common carrier was designed for both stages to simplify production and save cost. The first stage employs two smaller die while the second stage has a single large die. To minimize costs, impedance matching is kept as simple as possible with no extra capacitors and no unnecessary use of carrier real estate. In fact, the carrier could be modified to be even smaller for further ease of integration and cost savings.

The carriers were soldered on a copper baseplate for characterization purposes only. All transistors have been optimized, measured and characterized-with the help of a load-pull test bench.2

The input/output device impedances were measured with a commercial vector network analyzer calibrated with an short-open-load (SOL) technique based on a custom microstrip calibration standard kit.3

The synthesis and design of the input/output matching networks was performed with the help of commercial electronic-design-automation (EDA) circuit simulation software, the Advanced Design System (ADS) software suite from Agilent-EEsof (Santa Rosa, CA). The output of the first stage is matched directly to the input of the second stage to achieve a high level of integration and provide wideband impedance matching. As is the case with most large-signal transistors, the higher-power transistors of the second and third stages are intrinsically more difficult to match for broadband operation. Because these stages must be matched and properly isolated without the use of an additional isolator, fine tuning of these stages would be required.

The interstage matching between the second and third stages is less difficult to perform since it is possible to achieve a good impedance match at the output of the second stage. The output of this stage then drives two third-stage transistors. A compact Wilkinson power divider was developed for the purpose of splitting off the second-stage signals. It should be noted that a 50-ohm Wilkinson divider has high (70.7-ohm) impedance lines, although the impedance of the amplifier's second stage output and especially the input of the third stage are very low. Therefore, it would be necessary to design a divider with terminal impedances of less than 50 ohms, although not too low as to increase the size of the design. A value of 25 ohms was selected as a reasonable compromise; that particular value also allows the use of a common 50-ohm load resistor (Fig. 3).

For the third stage's output power combiner, the design was also made compact through the use of 25-ohm input ports in order to keep small the quarter-wavelength impedance lines. In addition to being a power combiner, it serves as a 25-to-50-ohm transformer, shifting the low impedance of the third-stage devices to the required 50 ohms for connection to other circuitry (Fig. 4).

The divider and combiner were computer optimized through 3.4 GHz to make sure that they provided high performance at the high-frequency end of the band. Even though some 50-to-25 ohms quarter-wavelength transformers were designed for test purposes (Fig. 5), they were found difficult to characterize without having their own influence on the test system. The actual divider and combiner produced for the amplifier were found to require no fine tuning, even without the use of an electromagnetic (EW) simulation tool (Fig. 6). The simulated performance of the combiner's isolation is slightly worse that that of the divider, due to the fact that the combiner is also an impedance transformer (Fig. 7).

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For the final design, the carriers soldered to a low-cost, highpermittivity (dielectric constant of 10.2) Teflon-based substrate suited for the amplifier. The carriers and circuit boards are mounted to a lightweight aluminum baseplate with 2.5-mm thickness. This provides enough rigidity without adding excessive weight. Due to the use of the bare die, very high circuit density is possible.

The shapes of the combiner and divider have been chosen for a high level of integration and to achieve high circuit density (Fig. 8, top). The circuit measures a compact 75 × 25 mm. Circuit grounding was also achieved through a low-cost approach. Traditional plated viaholes are difficult and expensive to realize in an aluminum baseplate. The circuit is therefore grounded through the use of special washers at the level of each screw. This simple solution provides a very good DC/RF ground and should help decrease the manufacturing's cost by avoiding a viahole realization process not easy to perform with aluminum.

For environmental protection, a global-plastic package was used over the three stages (Fig. 8, bottom). The package is simply glued onto the low-cost substrate with good adhesion. Measurement performed before and after packing showed that the plastic package has a negligible impact on the amplifier's performance. The use of the plastic cover allows the elimination of expensive ceramic transistor packages,4 and the shape of the global package still allows fine tuning on strategic areas on the amplifier circuit board. Following fine-tuning, the output power and efficiency were measured and found to exceed the minimum design requirements. The output power, for example, was slightly below 100 W at 2.9 GHz for the specified input level (0.6 W), but reached as much as 115 W output power at 3.0 and 3.1 GHz (Fig. 9). The third-stage collector efficiency exceeded 42 percent at 2.9 GHz and remained above 38 percent at 3.1 GHz. The collector efficiency remained predictably stable for a wide range of input-power levels from about 0.5 to more than 0.6 W.

The three-stage amplifier design demonstrates the feasibility of a transistor-die-based HPA for future radar transmit/receive (T/R) modules. The combination of unpackaged transistors and some practical design techniques help shave the cost and the size of the S-band amplifier without sacrificing performance.

The authors would like to thank H. Mollee for the transistor dice, J.-M. Coupat for design help with the carriers, A. Clérambour, Y-M. Crêté, and R. Préjant for prototyping help with the amplifier, and J.-P. Sipma for fruitful discussions.

1. Ph. Eudeline, P. Perez, "New generation low-cost S-band high power solid state transmitter for air traffic control and naval applications radars," International Radar Symposium 98, Munich.

2. Christos Tsironis, "A computer controlled tuner for accurate oscillator load-pull measurement," Microwave Journal, pp. 314-316, May 1991.

3. Pierre Bertram, "Fast and Accurate High Power Device Characterization with a Microstrip SOL Method," Microwave Journal, Vol 46, No. 5, May 2003.

4. Pierre Bertram, J-M. Coupat, J-P Sipma, Ph. Eudeline, N. Lande, F. Petrullo, and P. Coulon, "Conception d'un amplificateur hybride 100Wc bande S à puces nues pour radar à antenne active," Journées Nationales Microondes 2001.

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