While FinFET has its benefits, it also comes with some challenges. (Photo courtesy of TSMC.)

Product Makes Cut for 16-nm FinFET Reference Flow

Nov. 11, 2013
A line of design tools that address noise impact issues in SoCs has completed methodology innovations to be included in three-dimensional transistor architectures.

In advanced technologies, managing the power-integrity and electromigration (EM) reliability issues associated with high drive current has posed a continuous problem for chip designers. To help design teams tackle this obstacle, the RedHawk and Totem products from ANSYS subsidiary Apache Design have completed methodology innovations to be included in Taiwan Semiconductor Manufacturing Co.’s (TSMC’s) reference flow for 16-nm FinFET technology.  TSMC’s FinFET three-dimensional transistor architecture vows to enable the design of higher-performing and lower-power integrated circuits (ICs).

The reference flow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification. It promises to potentially provide  a 50% performance increase compared to a 28-nm process. Aside from the key application of system-on-a-chip (SoC) development, the architecture can be used for speed/power product requirements in central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), and field-programmable gate arrays (FPGAs). It also may suit networking and mobile computing applications, such as smartphones and tablets.

The integration of both the RedHawk and Totem tools into the TSMC 16-nm FinFET reference flow provides IR drop analysis, EM verification, and metal-insulator-metal-capacitor (MiMCap) insertion analysis. It also increases overall integration with implementation tools in the design flow. TSMC’s 3D-IC reference flow features transient thermal analysis, thermal-aware EM flow, global chip/package decoupling capacitance co-optimization, and simultaneous-switching-noise (SSN) analysis for vertically stacked die.

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