LDMOS FETs Power Efficient Doherty Amps

The eighth generation of a high-voltage LDMOS transistor process delivers high-power devices that are well suited to the needs of Doherty amplifiers for cellular base stations.

Doherty amplifiers have risen from obscurity to become the architecture of choice for many wireless networks, from multicarrier GSM to Long Term Evolution (LTE) cellular systems. Most of these amplifiers rely on laterally diffused metal-oxidesemiconductor (LDMOS) field-effect transistors (FETs), which meet the performance, reliability, and cost requirements of this intensely cost-sensitive market. The transistors produced by the eighth-generation, high-voltage (HV8) LDMOS process from Freescale Semiconductor (www.freescale. com) have been optimized for use in Doherty amplifiers. To demonstrate what the process can achieve in gain, efficiency, and RF output power, a Doherty amplifier based on the MRF8S21100 100-W LDMOS FET has been designed and evaluated under typical operating conditions.

For those unfamiliar with the Doherty amplifier, it was created in 1936 by W.H. Doherty of Bell Telephone Laboratories when he was trying to find ways to improve traveling-wave-tube-amplifier (TWTA) performance. The result was an architecture that inherently has very high power-added efficiency with input signals that have high peak-to-average ratios (PARs). There wasn't much call for these properties in the ensuing years because the predominant modulation techniques in mobile communication systems, such as frequency modulation (FM), Gaussian minimum shift keying (GMSK), and enhanced data rates for GSM evolution (EDGE), didn't require them.

But modern requirements are much different, since every current or emerging wireless system including WCDMA, WiMAX, and LTE produces high-PAR signals. As a result, the Doherty amplifier is appealing to service providers that must increase efficiency and lower operating expenses, since it can deliver efficiency increases of 14 percent or more when compared to parallel Class AB amplifiers.

A classic Doherty amplifier (Fig. 1) consists of two amplifiers: a carrier amplifier biased to operate in Class AB mode, and a peaking amplifier biased to operate in Class C mode. A power divider splits the input signal equally to each amplifier with a 90-deg. difference in phase. After amplification, the signals are recombined with a power combiner. When the amplifier's drive level is less than a specific value, only the Class AB carrier amplifier provides amplification and is presented with a load impedance that produces high efficiency and gain.

When the input signal peaks (as is the case with high-PAR signals), the Class C peaking amplifier also begins to deliver amplification to handle the highest power output levels, and produces a load impedance that allows both amplifiers to provide the highest possible output power.

However, a Doherty amplifier produces slightly less linearity and RF output power than a Class AB amplifier. Digital predistortion (DPD) linearization is typically used to restore linearity. Consequently, some transistor characteristics must also be optimized to maximize the linearity benefits brought by today's digital pre-distortion systems. Finally, in order to simplify the bill of material (BOM) for the amplifier, the same RF power transistor must be able to accommodate the requirements of both the carrier and peaking amplifiers.

To optimize the HV8 process for Doherty amplifier service, Freescale focused on improving a variety of parameters, including power density (watts/mm of gate periphery), capacitance reduction (pF/mm of gate periphery), higher efficiency (power-added efficiency at 1-dB gain compression), and improved linearity. Compared to a similar-sized HV7 device, HV8 devices typically offer 15-to-20-percent higher watts/mm. This translates into reduced capacitance/watt and higher impedances, as well as improved broadband performance at a given power level. An HV8 device also has 1-dB gain compression efficiency that is 4-to-5-percent higher than an HV7 device, as well as improved raw and DPD-correctable linearity as reflected in AM/PM phase distortion one third to one half that of HV7 devices.

Although HV8 device improvements offer better performance in traditional Class AB high-power amplifiers, the HV8 process has been tailored to dramatically enhance the linear efficiency in a Doherty amplifier configuration, which is the yardstick used by base station manufacturers to benchmark semiconductor vendors.

To show how its HV8-based LDMOS FETs can deliver high performance in Doherty applications, Freescale has performed tests using the MRF8S21100H in symmetrical Doherty amplifiers that are typical of those in service in wireless networks. The MRF8S21100H transistor is housed in a standard NI780 package and has a power capability in excess of 100 W at +28 VDC drain voltage.

The Doherty amplifier (Fig. 2), which uses two MRF8S21100H FETs, was subjected to a series of tests using multicarrier signals, since this has become the norm in high-data-rate applications, and presents a "worst-case" test scenario. The two 5-MHz carriers are separated with blanking in a "1 0 1" configuration that generates greater amounts of distortion and stresses the DPD circuit to ensure it can correct for nonlinearity. The stimulus signal has a 6.5 dB PAR, which is also realistic of typical crest factor reduction capabilities.

Measurements were made with drive levels backed off 8 dB from peak power, since providing 1.5 dB headroom above the 6.5-dB PAR is the desirable operating condition for most DPD systems. At this level, gain of the amplifier across the band, from 2.11 to 2.17 GHz, was 15.5 dB, and amplifier drain efficiency varied from a minimum of 45 percent to a maximum of 47 percent at any point in the band (Fig. 3). The real-time DPD circuit corrects IMD3 products to -55 dBc or better across the band. The amplifier's RF output power is 35 W while maintaining high linearity, as shown in Fig. 4.

The tests demonstrate what can be achieved using the MRF8S21100H in a typical Doherty amplifier and how LDMOS technology can be successfully optimized to deliver W-CDMA efficiency figures close to 50 percent without resorting to expensive semiconductor technologies such as GaN. The HV8 process clearly establishes a new performance/ price point and opens the door to additional reductions in power consumption by using more sophisticated Doherty amplifiers such as asymmetric and multistage configurations coupled with advanced DPD systems.

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