CMOS LNA Aids UWB Receivers

CMOS LNA Aids UWB Receivers

This broadband low-noise amplifier design provides more than 16-dB small-signal gain from 3 to 11 GHz based on a standard silicon CMOS semiconductor process.

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The broad swath of spectrum (7500 MHz) allocated by the United States Federal Communications Commission (FCC) in 2002 in the 3.1 to 10.6 GHz range creates many opportunities for new communications systems and their components.1 The benefits of such ultrawideband (UWB) radios include low-power operation, high data rates (to 1 Gb/s), reduced interference, and low cost.

One of the key component blocks in these radios is the low-noise amplifier (LNA), which must meet several stringent requirements—including broadband input matching, flat and high power gain, low noise figure, high linearity, and low power consumption. The design of such an amplifier can be a great aid to these UWB radios and systems.

Common-source and common-gate LNAs
1. These are versions of (a) a common-source (CS) LNA and (b) a common-gate (CG) LNA.

A number of UWB LNAs have been developed based on CMOS technology.2-8 The distributed amplifier (DA) has been one of the more popular architectures for this application. Since DA LNAs provide good wideband input matching, flat gain, and generally high input third-order intercept (IIP3) performance, they are well suited to these UWB applications.2-4 But DA LNAs consume a great deal of power with relatively low power gain in a large chip area.

Resistive feedback is a good solution for obtaining wide bandwidth and flat power gain.5-7 However, the use of a resistor in the feedback path reduces the power gain and degrades noise performance. One recent LNA topology of note is the cascode configuration with a Chebyshev input matching filter, which provides good wideband input matching and high power gain8; however, the noise figure is degraded by the filter’s insertion loss.

One challenge for UWB LNAs is posed by the linearity requirements, owing to the large numbers of in-band interference sources in that frequency range and the cross-modulation/intermodulation caused by blockers or transmitter leakage in a reconfigurable receiver.9 Furthermore, while the transmit frequency (fT) increases with technology scaling, linearity tends to degrade due to lower supply voltages in use and high-field mobility effects.9 This makes wideband linearization important.10,11

Linearization techniques which optimize overdrive voltage (Vgs - Vth) can be used to obtain peak IIP3. However, the bias voltage range for peak IIP3 is narrow, so that boosting linearity can be sensitive to process variations. The derivative super-position (DS) method12-14 uses an additional transistor’s nonlinearity to cancel that of the main device; it involves MOS transistors working in triode12 or in the weak inversion region13,14.

Therefore, using the DS method, it is difficult to match the transistors working in different regions, resulting in a linearity improvements that are highly sensitive to variations in pressure volume and temperature (PVT). The body biasing technique15 is suitable for improving linearity performance; unfortunately, it degrades gain and noise performances. In ref. 16, the post-distortion technique was used to improve linearity, with good results.

To achieve good performance for UWB systems, a common-gate (CG) LNA design is proposed. These LNAs offer simple input matching networks with good linearity and low power consumption compared to common-source (CS) LNAs. Because the power gain of a CS LNA tends to be low,17 a CS amplifier is used in this design as a second stage. The proposed LNA design employs current-reuse and forward body biasing techniques to achieve low power consumption. In addition, shunt-series peaking techniques are used to extend the 3-dB bandwidth, and a post-distortion technique is employed to improve the linearity performance.

Based on their input matching characteristics, reported CMOS UWB LNA architectures can be divided into two major groups: CS and CG LNAs.18Figure 1 offers the two general topologies for these amplifier types. Figure 1(a) is a CS LNA that requires at least two inductors (Lg and Ls) for simultaneous noise and input matching (SNIM). Assuming the channel resistance, γ0, and the gate-drain parasitic capacitance, Cgd, are negligible, the CS LNA’s quality factor (Q) can be derived as:

Eq. 1-2

Substituting Eq. 2 into Eq. 1 yields Eq. 3:

Eq. 3

where:

ω0 = the resonant angular frequency of the input impedance;

gm = the transconductance of the metal-oxide-semiconductor field-effect transistor (MOSFET);

Lg = the gate inductor;

Ls = the source inductor; and

Cgs = the gate-source parasitic capacitance of the device.

The architecture is inherently narrowband because of the high Q value and the difficulty in achieving wideband input match to the signal source in the presence of the parasitic capacitances. Figure 1(b) shows a typical CG LNA. The input matching network of the CG LNA has a parallel resonance, and the Q of the CG LNA can be expressed as:Eq. 4-5

By substituting Eq. 5 into Eq. 4, QCG can be expressed by Eq. 6:

Eq. 6

Since Ls is intended to block the RF leakage to the ground, the Ls value of a conventional CG LNA is higher than that of a CS LNA, and the Qcs value is higher than the Qcg value. Obtaining a wideband input match and absorbing parasitic capacitances with a CG LNA is relatively simple, making this a suitable topology for UWB applications.

Proposed UWB LNA design
2. This schematic diagram shows the proposed UWB LNA design.

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Cutting Power Consumption

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Mobile and portable applications require low power consumption, and the most efficient approach for reducing power consumption is through power supply voltage scaling. In the proposed LNA circuit, the forward body biasing technique is employed to reduce the threshold voltage, Vth. The Vth for a MOSFET can be found from Eq. 7:

Eq. 7

where:

Vth0 = the threshold voltage when Vbs = 0;

γ = the body-effect coefficient;

σf = the surface potential; and

Vbs = the voltage between the body and the source.

Usually, Vbs ≤ 0, so Vth ≥ Vth0. To reduce Vth, Vbs is set greater than zero so that Vth < Vth0. The typical value of Vth is about 0.5 V. For the proposed LNA design, Vbs = 0.29 V and Vth = 0.43 V.  

The UWB LNA was designed and simulated in a standard 0.18-μm RF CMOS process. Figure 3 shows a schematic diagram of the proposed LNA, including the output buffer stage (M4, M5). The current-reuse configuration can be considered as a two-stage cascade amplifier, where the first stage is the CG amplifier (M1) and the second stage is the CS amplifier (M2).

CG diagrams
3. These schematic diagrams show the CG LNA input stage (a) circuit topology and (b) small-signal equivalent circuit.

The signal amplified by M1 is coupled to the gate of M2 by series resonance (Lg and Cg) while the source of M2 is bypassed by capacitor Cb. Besides, Cb determines the low-frequency band expansion and gain flatness. The circuit saves power through the reuse of the bias current.

Table 1

The CG topology LNA exhibits low power gain, so a CS amplifier is included in the second stage. It employs a gain peaking technique which consists of RL, LL, M2, and Lp. To reduce the threshold voltage of the transistor, the forward body biasing is employed. The post-distortion technique is used in the first stage (M3), reducing the nonlinearity of the main device (M1). Table 1 summarizes the circuit parameters of the proposed LNA.

Equivalent circuit
4. This schematic diagram shows the equivalent circuit of the proposed UWB LNA.

RF/microwave components and systems are typically designed for a standard impedance of 50 Ω, so the input stage of the UWB LNA should match to 50 Ω with minimal power reflection.21 For simplicity in this analysis, body effects are ignored. Figure 4 shows the CG input stage of the proposed UWB LNA, and the input impedance can be derived by Eq. 8:

Eq. 8

where:

Cta = the total capacitance at node a;

Ctb =  the total capacitance at node b;

Cgs1 = the gate-to-source capacitance;

gm1 = the transconductance;

r01 = the output resistance of M1; and

ZL = the CS stage equivalent load impedance.

As Eq. 8 indicates, the input impedance approximates 1/gm1 over the frequency band of interest. Transconductance gm3 << gm2, where gm2 and gm3 are the transconductances of transistor M2 and M3, respectively. The input impedance Zin(ω as seen from resistor Rs of the CG LNA is about the same with or without transistor M3 present, so that M3 cannot be considered to significantly affect the input impedance matching.

However, for a wideband input match, Eq. 8 indicates that gm1 of M1 in the CG stage should slightly exceed 20 mS. Through simulation, input matching is considered good when gm1 approaches 26 mS.

Input reflection coefficient
5. The plot portrays the amplifier’s input reflection coefficient (S11).

The achievable maximum power gain also depends on the output impedance matching. In the proposed LNA, a simple source follower, which consists of M4 and M5, is employed to obtain output impedance matching. If the source of M2 is perfectly grounded by Cb, the equivalent schematic of the proposed LNA can be redrawn in Fig. 5, where the proposed UWB LNA is created by the two-stage amplifier.

The first stage is a CG amplifier and the second stage is a CS amplifier. For simplicity, body effects are not considered. The voltage gain of the first stage, AV1, can be expressed by Eq. 9:

Eq. 9

where:Eq. 10-13

where:

gm1 = the transconductance of M1;

r01 = the channel resistance of M1;

RS = the input source resistance (50 Ω);

Cs1 = the source parasitic capacitance caused by Cgs1;

Cd1 = the drain parasitic capacitance caused by Cgd1;

CL1 = the parasitic load capacitance of the second stage; and

Z3 = the equivalent impedance of M3.

For simplicity’s sake, the direct-current (DC) blocking capacitors Cin and Cout are ignored in the analysis.

The voltage gain of the second-stage, AV2, is given by Eq. 14:

Eq. 14

where:Eq. 15-16

gm2, γ02, and CL2 are the transconductance of transistor M2, the channel resistance of M2, and the total load capacitance at the second-stage output, respectively. Additionally, Cd2 is the calculated parasitic capacitance at the drain of M2, which is produced by the gate-to-drain parasitic capacitor (Cgd2). The overall circuit frequency response of S21 has a good flatness and a high power gain because of the cascaded first and second stages.

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A Closer Look

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The first stage of a receiver typically includes an LNA and its noise figure is critical to the receiver’s performance, such as sensitivity, distortion, and signal range. For the purpose of simplicity, the parasitic effects, body effects, and the influence of M3 on the noise performance are ignored in this analysis. For the proposed LNA, the mean-square noise voltage and the mean-square noise current can be expressed by Eqs. 17-20:Eq. 17-20

which are produced by source resistor Rs and the channel noise of M1, M2, and load resistor RL. Parameters k, T, γ, and Δf represent Boltzmann’s constant, the absolute temperature (in degrees Kelvin), the thermal noise coefficient (having a value from 1 to 2 in the saturation region of a short channel MOSFET), and the noise bandwidth (in Hz), respectively.

The noise factor of the proposed LNA can be expressed by Eq. 21:

Eq. 21

where V2n,out is the total noise at the output and AV is the total voltage gain.

The total voltage gain AV can be obtained by Eqs. 17 and 21. From Eq. 21, it can be seen that the effects of gm1 and gm2 can be seen on achieving a lower noise factor; for low noise and low power consumption, gm1 should have a low value. But this can also have adverse effects on the total noise factor since low gm1 leads to low first-stage gain.

Alternately, from Eq. 21, it can be seen that a high gm2 value is beneficial for low noise factor, although the high value will also increase power dissipation. For best performance, the values of gm1 and gm2 should be optimized. Because both transconductance values depend on transistor width (W1 and W2, in the proposed LNA design, the optimal values of W1 and W2 are 124 and 48 μm, respectively.

The proposed UWB LNA was designed and simulated with the aid of the Advanced Design System (ADS) software from Agilent Technologies (now Keysight Technologies), using a standard 0.18-μm silicon RF CMOS process. With current reuse and forward body biasing, the supply voltage is only +1.3 VDC and the power consumption is only 3.1 mW.

Output reflection coefficient
6. This plot shows the amplifier’s output reflection coefficient (S22).

Figure 6 shows simulated input reflection coefficient (S11, which is less than -13 dB from3 to 11 GHz. Figure 7 shows simulated output reflection coefficient (S22), which is less than -14 dB from 3 to 11 GHz. Figure 8 shows voltage gain (S21) for the LNA, which ranges from 16.8 to 18.9 from 3 to 11 GHz. As a result of a shunt-series peaking technique, S21 shows high voltage gain with good flatness.

Gain performance
7. The S21 plots represent the proposed amplifier’s gain performance.

Noise figure
8. The plots show the proposed amplifier’s noise figure.

IIP3
9. This plot represents the proposed amplifier’s input third-order intercept point (IIP3).

Amplifier layout
10. This is the layout for the proposed UWB amplifier following computer simulation.

Figure 9 plots the noise figure of the proposed LNA, which ranges from 1.9 to 3.2 dB across 3 to 11 GHz. Figure 10 shows the layout of the proposed LNA, with total chip area of 0.87 × 0.81 mm2, including the input and output pads. Table 2 summarizes its performance and compares it with previous work.

Table 2

Acknowledgment

The authors would like to thank the research platform of the Open Fund Project for access to the coal mine monitoring network based on the wireless sensor networks in the Department of Education of Hunan Province, grant No. 12C0986.

Xu Xia, Professor

Hunan Vocational College of Security Technology, Changsha, 410151, Hunan Province, People’s Republic of China

Fengying Han, Professor

Changsha Aeronautical Vocational and Technical College, Changsha, 410014, Hunan Province, People’s Republic of China

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References

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