Design Loop Filters For PLL Frequency Synthesizers

By Ken Holladay
Applications Engineer

Dennis Burman
Marcom Manager

Fujitsu Microelectronics, Inc., 3545 North First St., San Jose, CA 95134; (800) 866-8608, FAX: (408) 324-1377, Internet: http://www.fujitsumicro.com

PHASE-LOCKED-LOOP (PLL) synthesizers are integral components in wireless communication transceivers. Many companies that are entering the wireless/RF marketplace are experiencing the challenge of designing a PLL synthesizer for the first time. To help them meet that challenge, this article will show that it is not difficult to design a high-performance PLL synthesizer using highly integrated, off-the-shelf parts.

The major goals in the design of a PLL frequency synthesizer are to achieve low phase noise, low spurious output, and the ability to step, or hop, from one frequency to another in a specified amount of time. These characteristics largely depend on the synthesizer's loop filter. Unfortunately for first-time loop-filter designers, most of the articles and books written on this subject dwell on theory and try to cover all cases of PLL-synthesizer design. This article narrows the focus to the design of a simple, passive three-pole loop filter typically used in low-voltage, low-operating-bandwidth synthesizer applications such as wireless transceivers.

The calculations presented here have been found to achieve the expected performance goals. If the information used in the calculations is accurate, the PLL synthesizer will perform as designed. Experience has shown that if the PLL synthesizer does not perform as expected, some component part or device specification is in error.

Due to current levels of semiconductor integration, most of the components that make up the synthesizer (Fig. 1)--the PLL, the reference oscillator, and the voltage-controlled oscillator (VCO)--are available as integrated circuits (ICs). The only external components that are needed are the DC-decoupling elements, RF bypass elements, and the passive loop-filter components.

Fig 1. This block diagram shows the basic PLL layout.

The simplified loop-filter design formulas, found in Fujitsu's Super PLL Application Guide, are detailed. The formulas are based on the use of a basic passive two-pole loop filter along with a single-pole spur filter (Fig. 2).

Fig 2. This schematic illustrates the loop-filter configuration.

The basic terms and definitions that are related to PLL synthesizers can be defined as follows:

F_step = the maximum frequency change during a step, or hop, from one frequency to another,

t_s = the desired time for the carrier to step to a new frequency,

f_a = the frequency of the carrier, within the desired time (t_s), after a step or hop--normally 1000 Hz,

= the damping factor (A value of 0.707 is typical.),

f_n = the natural frequency,

I_cp = the charge-pump current, and

K_vco = the VCO sensitivity.

The design of a basic PLL synthesizer loop filter follows a few simple calculations.

First, determine the maximum dividing ratio, N, by:

Then, calculate f_n from eq. 2:

The value of capacitor C2 must now be found from eq. 3:

Similarly, the value of resistor R1 can be found from eq. 4:

By knowing the value of C2, it is now possible to find C1.

The final step involves the calculations of resistor R2 and capacitor C3, which are used to create the spur filter. R2 and C3 are used to reduce any spurious energy caused by the reference frequency. The product of R2 and C3 should be at least one-tenth the product of C2 and R1.

As a design exercise, it is first necessary to define the basic synthesizer requirements for a sample application, and then define the specifications for the active components.

For this example, a hypothetical application with arbitrary low-side injection is specified. It uses a model MB15F08SL PLL IC from Fujitsu Electronics (San Jose, CA) and a VCO with a 25-V/MHz sensitivity. The application also requires a frequency range of 1675 to 1735 MHz, channel spacing of 200 kHz, maximum frequency hop of 60 MHz, a frequency hop time of 500 µs, and a frequency accuracy of 1000 Hz after the specified hop time.

The specifications for the active components are defined as follows: the VCO sensitivity is 25 MHz/V and the PLL IC charge-pump current is 6 mA.

Using the loop-filter equations, the synthesizer requirements, and the active-component specifications, the loop-filter component values can now be calculated.

Using eq. 1, N can now be calculated by:

Using eq. 2, f_n can be found by:

Using eq. 3, C2 can be determined by:

Using eq. 4, R1 can be calculated by:

Using eq. 5, C1 can be found by:

Finally, R2 and C3 (the spur filter) must be determined. The product of R2 and C3 should be approximately one-tenth the product of R1 and C2.

After the loop-filter values have been found (Fig. 3), the loop bandwidth can be calculated. Knowing the loop bandwidth will help determine if the PLL is operating correctly when the phase noise is displayed on a spectrum analyzer.

Fig 3. The loop-filter component values are rounded to the nearest standard values.

The loop bandwidth is calculated using the following equation:

Using the values determined earlier, the loop bandwidth for this example is:

Fig 4. The excellent phase-noise performance of the RF PLL of Fujitsu's new MB15F08SL dual 2.5/1.2-GHz PLL is illustrated using the calculated loop-filter values.

The performance of the PLL synthesizer with the calculated values were measured with a spectrum analyzer and plotted (Figs. 4 to 6).

Fig 5. The 200-kHz spurious signals are shown to be an impressive -87.7 dBc, typical of the new Fujitsu SL series of advanced PLL synthesizers, providing optimum performance for the latest digital wireless communications designs.

The graphs confirm that the calculations work well when designing loop filters to be used in many modern PLL applications.

Fig 6. It takes 514 µs to change the frequency from 1675 MHz to 1735 MHz ±1000 Hz.

Marker "0" shows the phase noise inside the loop to be -80.5 dBc/Hz. Marker "1" shows that the loop bandwidth is approximately 1.65 kHz.

An important part of the loop-filter design is using components that will not degrade the performance of the PLL synthesizer. Capacitors must have very-low leakage. Ceramic capacitors should not be used, since the piezoelectric effects may cause noise and even microphonics on the VCO tuning line. Film capacitors are recommended. The resistors should consist of metal or carbon film. Resistors that are composed of carbon are not recommended.

The layout of the printed-circuit board (PCB) can affect the level of VCO spurious signals and noise. When laying out the PCB for minimal noise, two things are important. First, provide the shortest possible ground path between the PLL IC ground pins, loop-filter ground, as well as the ground for the VCO varicap tuning diode. If a packaged VCO is used, it should be mounted close to the PLL IC and loop filter. Second, bypass the V_CC lines that feed the PLL chip with a small-value capacitor (0.1 µF) and a large-value capacitor (10 µF). These capacitors should be placed as close as possible to the V_CC pins. Bypassing should also be used for the VCO. If the PLL and the VCO use the same value for V_CC, a 22- resistor should be placed in the V_CC line between them in order to improve the isolation.

Synthesizers that operate well above 2000 MHz can be manufactured with relatively few problems--as long as good RF techniques are used for board layout and parts placement.

Vadim Manassewitsch, Frequency Synthesizers, John Wiley & Sons, Inc.