PLL Synthesizers Suit Low-Power Wireless Systems

By Mike Curtin
Staff Applications Engineer

Paul O'Brien
Senior RF Test Engineer

Analog Devices B.V., Raheen Industrial Estate, Limerick, Ireland; +353 61 495488, FAX: +353 61 304094, Internet: http://www.analog.com

PHASE-LOCKED-LOOP (PLL) frequency synthesizers maintain frequency stability in wireless handsets and, as a matter of course, consume battery power in the process. But wireless handsets are shrinking and so are their batteries. For handset designers, this shrinkage means a reduced power budget, which forces them to seek components that draw as little current as possible. To answer this need, Analog Devices, Inc. (Wilmington, MA) has developed a new generation of integer-N PLL synthesizer that conserves power without compromising performance.

The synthesizers are segregated into two families--the ADF4110 family and the ADF4210 family. The main difference between the two is that the ADF4110 family has a complementary RF input, while the ADF4210 family has an RF input and an intermediate-frequency (IF) input.

This article examines various wireless architectures and shows how this new type of synthesizer fits those architectures. The discussion presents phase-noise and reference-spur performance, and shows how features such as a programmable charge-pump current can help keep the loop bandwidth constant under varying loop conditions.

The ADF4110 family of PLL synthesizers (Fig. 1) has four members- the ADF4110, ADF4111, ADF4112, and ADF4113.

Fig 1. This block diagram shows the functional components of the ADF4110 family of PLL synthesizers.

Functionally, they are identical. The major difference among them is maximum operating frequency. The ADF4110 operates to 550 MHz; the ADF4111 to 1.1 GHz; the ADF4112 to 2.8 GHz; and the ADF4113 reaches 3.7 GHz.

The synthesizer's frequency-reference input (REF_IN) feeds a 14-b counter, which can derive all of the commonly used channel-spacing frequencies from off-the-shelf temperature-controlled crystal oscillators (TCXOs). In the case of Global System for Mobile Communications (GSM) network, for example, a 13-MHz TCXO is often used as the system reference. Setting the reference divider to 65 provides the required 200-kHz channel spacing.

The complementary RF input (RF_INA and RF_INB) supports a balanced signal. More often, an unbalanced RF signal from a voltage-controlled oscillator (VCO) is fed to RF_INA, and RF_INB is grounded through a small bypass capacitor. The RF input leads to the N divider, which sets the output frequency. The divider consists of a dual-modulus prescaler (programmable for divide ratios of 8/9 or 32/33) followed by a 6-b A counter and 13-b B counter. The combination of programmable prescaler, 6-b A counter, and 13-b B counter yields three overlapping divide-ratio ranges. These ranges are 56 to 65591 (prescaler of 8/9); 240 to 131119 (prescaler of 16/17); and 992 to 262175 (prescaler of 32/33).

The phase/frequency detector (PFD)/charge-pump output current (I_CP) is programmable in binary steps from 5 mA to 625 µA. Additionally, the absolute value of I_CP can be varied by changing the value of the R_SET resistor. For full-scale current of 5 mA, R_SET must be 4.7 k. As this resistor value is varied, I_CP changes proportionately. Having the ability to vary I_CP enables the user to optimize the loop response on the fly. For example, many wideband VCOs have sensitivities that vary dramatically over the full frequency band of operation. By having the ability to program the I_CP value, it is possible to compensate for this widely varying sensitivity and maintain good loop stability over the full frequency range. It is also possible to set anti-backlash pulse width in the PFD. The three anti-backlash settings are 1.3, 2.9, and 6.0 ns.

The ADF4210 family of PLL synthesizers (Fig. 2) has three members- the ADF4210, ADF4211, and ADF4212.

Fig 2. This block diagram shows the functional components of the ADF4210 family of PLL synthesizers.

Each of these has an IF synthesizer capable of operating to 510 MHz. As with their cousins, the members of this family differ mainly in their maximum RF operating frequency. The ADF4210 operates to 1.2 GHz; the ADF4211, 2.0 GHz; and the ADF4212, 3.0 GHz. And similar to the ADF4110 family, the ADF4210 family offers programmable prescaler, programmable I_CP, as well as programmable anti-backlash pulse width.

The ADF4110 and ADF4210 families both exhibit very good phase-noise and reference-spur performance. The ADF4110 family is more likely to be used in the transmitter sections of handsets and base stations where there is generally just one upconversion stage. The ADF4210 family is best suited to receiver designs where two downconversion stages are needed. In all of these applications, low power consumption is critical. The ADF4212's typical I_DD of 7 mA and maximum frequency of 3 GHz makes it ideal for wideband code-division-multiple-access (WCDMA) receivers. The ADF4211's typical I_DD of 5 mA and maximum frequency of 2 GHz is ideal for DCS-1800 receivers. The ADF4112 has a typical power I_DD of 3 mA and is ideal for DCS-1800 transmitters.

Figure 3 shows the ADF4112 being used to generate the local-oscillator (LO) signal in a DCS-1800 handset application.

Fig 3. This schematic shows how the ADF4112 can be used as part of the local oscillator (LO) for a DCS-1800 handset transmitter.

The reference-input signal is applied to the circuit at FREF_IN and is terminated in 50. In a GSM or DCS-1800 system, the frequency of this reference input is typically 13 MHz. To achieve a channel spacing of 200 kHz (the DCS-1800 standard), the reference input must be divided by 65 using the ADF4112's on-chip reference divider.

The ADF4112 is capable of reaching 2.8 GHz. In this integer-N synthesizer, N can be programmed from 56 to 262,000 in discrete integer steps. In the case of the handset transmitter, which requires an output range of 1710 to 1785 MHz, and where the internal reference frequency is 200 kHz, the desired N values range from 8550 to 8925.

The charge-pump output of the ADF4112 (pin 2) drives the loop filter. When calculating the loop-filter component values, a designer must consider a number of items. In this example, the loop filter is designed so that the overall phase margin for the system is 45 deg. Other PLL system specifications include the following items: Kd (the charge-pump current of the ADF4112) = 5 mA; Kv (the sensitivity of the MQE524-1747) = 50 MHz/V; a loop bandwidth of 12 kHz; a reference frequency (FREF) of 200 kHz; N = 8700 (midrange value), and an extra reference-spur attenuation of 10 dB. All of these specifications were used to calculate the loop-filter component values shown in Fig. 3.

The loop-filter output drives the VCO. The VCO output is fed back to the RF input of the PLL synthesizer and also drives the RF output terminal. A T-circuit configuration using 18- resistors provides 50- matching impedance at the VCO output, RF output, and RF_IN terminal of the ADF4112.

In a PLL system, it is important to know when the system is locked. In Fig. 3, this is accomplished by using the ADF4112's MUXOUT signal. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. For example, the MUXOUT can be programmed to monitor the lock-detect (LD) signal, and can be used to initiate the power ramp sequence.

The ADF4112 uses a simple four-wire serial interface to communicate with the system controller. The reference counter, N counter, as well as various other on-chip functions are programmed through this interface.

In Fig. 3, the output VCO is the MQE524-1747 from Murata Electronics (Smyrna, GA). This device was specifically chosen for the transmitter section due to its high output-power level. It runs from a supply of +3.8 VDC and delivers a typical output level of +10 dBm. For newer designs that might require a lower operating voltage, the MQE9PE-1747 is recommended. It runs from a supply voltage of +2.75 VDC and delivers a typical output-power level of +7.5 dBm. Note that the sensitivity of the MQE9PE-1747 is 70 MHz/V, compared to 50 MHz/V for the MQE524-1747. The designer must take this into account when calculating the loop-filter components.

Figure 4 illustrates the phase-noise plot for Fig. 3.

Fig 4. This graph shows the phase-noise performance of the circuit in Fig. 3.

The frequency and phase noise were measured over a 5-kHz span. As already stated, the reference frequency used was FREF = 200 kHz and the output frequency was 1747 MHz (N=8735). If this were an ideal PLL synthesizer, a single discrete tone would be displayed along with the spectrum analyzer's noise floor. But the real-world circuit exhibits the tone and the phase noise generated by the PLL components. The loop-filter values were chosen to provide a loop bandwidth of approximately 12 kHz. The flat part of the phase noise for frequency offsets less than the loop bandwidth is actually the phase noise generated by the synthesizer. It is specified at a 1-kHz offset. The value measured was -86.30 dBc/Hz. This is the phase-noise power in a 1-Hz bandwidth. The authors arrived at this figure by considering the following factors:

1. The spectrum-analyzer marker shows the relative power in dBc between the carrier and the sideband noise at 1-kHz offset.

2. The spectrum analyzer displays the power for a certain resolution bandwidth (RBW). In the plot, a 10-Hz RBW is used. To represent this power in a 1-Hz bandwidth, 10 log (RBW) must be subtracted from the value in item 1.

3. It is necessary to add a correction factor that takes into account the implementation of the RBW, the log-display mode, and detector characteristic of the spectrum analyzer.

Phase-noise measurement with spectrum analyzers such as the HP 8561E from Hewlett-Packard Co. (Palo Alto, CA) can be made quickly by using the marker-noise function, MKR NOISE. This function takes into account the previously mentioned three factors and displays the phase noise in dBc/Hz.

The phase-noise measurement mentioned previously is the total output phase noise at the VCO output. To estimate the contribution of the PLL device (noise due to phase detector, R&N dividers and the phase-detector gain constant), divide the result by N2 (or subtract 20 logN from the above result). This provides a phase-noise floor of [-86.30 - 20 log(8735)] = -165.1 dBc/Hz.

In an integer-N PLL (where the output frequency is an integer multiple of the reference input), reference spurs are caused by the fact that there is continuous update of the charge-pump output at the reference-frequency rate (Fig. 5).

Fig 5. This graph shows the reference spurs for the circuit in Fig. 3.

Consider the basic model for the PLL. When the PLL is in lock, the phase and frequency inputs to the PFD (F_REF and F_N) are essentially equal. In theory, one would expect that there would be no output from the PFD in this case. In effect, the loop would be broken and the output could drift. To prevent this, the PFD is designed so that in the locked condition, the current pulses from the charge pump are equal in magnitude and duration (Fig. 6). Any difference in up and down duration will provide charge to the loop filter at the reference rate, thus causing ripple on the VCO control input, which, in turn, causes ouput spurs.

Fig 6. This graph shows the output current pulses from the PFD charge pump.

It is possible to detect reference spurs using a spectrum analyzer simply by increasing the span to greater than twice the reference frequency (Fig. 5). In this case, the reference frequency is 200 kHz, and the diagram shows that reference spurs at ±200 kHz from the center frequency output are -83 dBc.

Figure 7 shows the circuit for the LO section of a WCDMA receiver.

Fig 7. This schematic demonstrates how the ADF4212 can be used as part of the LO for a WCDMA receiver.

In this design, the system power supply is +3 VDC. The total power typically consumed by the VCOs and the synthesizer is estimated to be 70 mW (45 mW by the VCOs and 25 mW by the synthesizer). There are two down-conversion stages. The first stage takes the signal in the 2070-to-2130-MHz band and converts it down to 230 MHz. This is then further translated to the baseband by the MQE744-233B VCO.

Figure 8 shows that the phase noise is -78.86 dBc/Hz at an offset of 1 kHz.

Fig 8. This graph shows the phase-noise performance for the circuit in Fig. 7.

Working back to calculate the synthesizer noise based on this value, the result is -161 dBc/Hz. It is interesting to note that this is several decibels away from the -165-dBc/Hz value resulting from the DCS-1800 design (Fig. 3). This is because the circuit in Fig. 7 is a full +3-VDC design. The output levels from the VCOs are typically 0 dBm, compared to +10 dBm from the VCO in Fig. 3. The first reference spurs (200 kHz) are below -82 dBc, and the second reference spurs (400 kHz) are below -90 dBc (Fig. 9).

Fig 9. This graph shows the reference-spur performance for the circuit in Fig. 7.

Many of the wireless applications for synthesizers and VCOs in PLLs are narrowband in nature. These include the various wireless standards such as GSM, DCS-1800, CDMA, and WCDMA. In each of these cases, the total tuning range for the LO is approximately 100 MHz. However, there are also wideband applications where the LO could have up to an octave of tuning range. For example, cable-TV (CATV) tuners have a total range of approximately 400 MHz. Figure 10 shows a wideband-LO application that uses the ADF4113 (3.8-GHz bandwidth) to control and program the Micronetics M3500-2235.

The loop filter was designed to have an RF output frequency of 2900 MHz, a loop bandwidth of 100 kHz, a PFD frequency of 1 MHz, an ICP of 5 mA, and a VCO KD of 90 MHz/V (which is the sensitivity of the M3500-2235 at 2900 MHz).

In narrowband applications, there is generally a small variation in output frequency (generally less than 10 percent) and also a small variation in VCO sensitivity over the range (typically 10 to 15 percent). However, in wideband applications, both of these parameters have a much-greater variation. Figure 10, for example, shows -25- and +17-percent variation in the RF output from the nominal 2.9 GHz. The sensitivity of the VCO can vary from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz (+33 percent, -17 percent). Variations in these parameters will vary the loop bandwidth. This, in turn, can affect stability and lock time. By changing the programmable I_CP, it is possible to compensate for these varying loop conditions and ensure that the loop is always operating close to optimal conditions. The circuit shown in Fig. 10 was verified over the frequency range of 2200 to 3400 MHz, and maintained lock under these conditions.

Fig 10. This schematic demonstrates how the ADF4113 can be used in a wideband LO.

This new generation of integer-N PLL synthesizer provides low-noise performance for wireless applications without the large power consumption associated with frequency synthesizers. Analog Devices, Inc., One Technology Way, Norwood, MA 02062-9106; (800) 262-5643, Internet: http://www.analog.com.

The authors would like to acknowledge the following people: Bill Hunt (Analog Devices, Inc.) and Brendan Daly (Analog Devices, Inc.) and Lorraine Kearn (Murata Manufacturing Co.) for technical support on the Murata VCOs.