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[Components]
Designing A Low-Noise VCO
An inductance-capacitance (LC) voltage-controlled oscillator (VCO) configuration can provide wide tuning range with low power consumption and low phase noise.

Andreas Laute, Jeff Peter, Peter Teichmann  |  ED Online ID #9181 |  November 2004

Transmitters and receivers for license-free industrial-scientific-medical (ISM) and short-range-device (SRD) bands require fairly high-performance voltage-controlled oscillators (VCOs). For example, ISM and SRD integrated circuits (ICs) must meet the emission limits a such standards as EN 200 220-1, FCC part 15, and ARIB STD-T67. Ring-oscillator1 and relaxation-type VCOs are limited in their ability to support narrowband applications with high output levels at low cost. But inductor-capacitor (LC)-based VCOs can provide good performance at the low costs required by these competitive license-free applications.

Such applications can suffer from several sources of spurious emissions. For example, there are three main sources in a typical phase-locked-loop (PLL)-based transmitter (Fig. 1). The noise of the charge pump is dominant inside the PLL bandwidth. This noise is translated to phase noise via the VCO gain. Outside the loop bandwidth, the noise of the free-running VCO is the dominant noise contributor. VCO phase noise is suppressed inside the loop bandwidth. The third source of spurious emissions is the reference feedthrough signal. It is caused by the nonideal (nonlinear) switching of the charge pump, which leads to a ripple current at the output of the charge pump. As with the VCO phase noise, the reference spurious signals are suppressed by the loop filter.

There are several trade-offs to meet the spurious emission limits. In a ring-oscillator-based VCO, phase noise close to the carrier is usually reduced by the PLL's feedback loop, which has a high bandwidth. But since the loop filter is also designed to suppress reference spurious signals, this leads to problems if high output powers are desired. Furthermore, the noise contribution of the charge pump might be a problem. A better approach involves the use of an inductor-capacitor-based VCO (LC-VCO). Because LC-VCOs have lower phase noise than ring-oscillator VCOs, the bandwidth of the loop filter can be reduced to achieve better suppression of the reference spurious signals, without compromising phase noise close to the carrier. The lower loop bandwidth also reduces the contribution of the charge pump noise.

A similar problem exists for narrowband operation. With an integer-N PLL, narrow channel spacing requires a low reference frequency and narrow loop-filter bandwidth. Therefore, an LC-VCO is necessary when good phase-noise performance close to the carrier is required. Outside the loop bandwidth, the phase noise of the transmitter is only as good as the free-running VCO's phase noise. This is true regardless of the PLL topology.

One way to overcome this problem is the use of an LC-based VCO with an external inductor. By moving the inductor off chip, a smaller IC is possible and higher quality factor (Q) for the inductor. Disadvantages include are increased pin and external component count, increased LC tank parasitics, and the risk of multimode oscillations. These problems cannot be solved by proper IC design alone, but require proper printed-circuit-board (PCB) layout and selection of suitable external components. An LC-VCO with external inductor can save chip area and cost less than an integrated solution, but requires more labor on the part of the user. Thus, a fully integrated LC-VCO is preferred.

A high-quality inductor is critical for the design of a low-power low-phase-noise LC-VCO. Inductors are, however, not readily available in standard integration technologies. One possibility is to use bond-wire inductors. Bond-wire inductors require a length of roughly 1 mm/nH inductance. Because die sizes must be quite small in the competitive market of ISM applications, the realizable inductance values are too small for frequencies as low as 900 MHz.

Therefore, an integrated inductor that uses the metallization system of the integration technology is required. For inductors with a high quality factor, a metal layer with a low resistance is needed. A high substrate resistance is desirable in order to reduce the substrate losses. The used 0.6-µm BiCMOS process offers a power metal option. The third metal layer has a thickness of 2.4 µm and a sheet resistance of 12.5 Ω/square. It is placed 3.5 µm above the substrate. The substrate resistance is 20 Ω-cm.

The VCO is designed with a single inductor to conserve chip area. The inductor is used differentially to achieve a high Q factor. This is also a good match to the differential VCO topology. There exists, however, no support for symmetrical inductors in the Cadence Inductor Modeller.2 Therefore, the inductor was modelled as a non-symmetrical inductor, and the model was then modified according to the several simple approximations. Since the average position of the turns does not change for symmetrical inductors, the inductance value of a symmetrical inductor is approximately the same as for a non-symmetrical inductor with the same geometry. The quality factor will be slightly lower, because of the increased number of via holes. This is modelled through an increased series resistance.

The self-resonant frequency will be significantly smaller, because the oxide capacitance between two adjacent turns now has a much greater contribution to the inductor's parasitic capacitance. Simple estimations suggest that the self resonant frequency of our inductor is only 70 percent of the corresponding non-symmetrical inductor. This is modelled with an additional parallel capacitance. Figure 2 shows the inductor layout and its properties.

The second part of the LC tank is the integrated varactor. In the used process, integrated varactor diodes are readily available. They make use of the junction between a P-diffusion area located in an N-well. The buried collector and sinker are used to achieve a low series resistance for the N-well. The quality factor of the varactor diodes depends on the tuning voltage. At 900 MHz and for a tuning voltage of 2 V, the Q is 70, and reduces to about 35 for a tuning voltage of 0 V.

The cathode of the varactor is located in the N-well, and carries a considerable parasitic capacitance. This parasitic capacitance has a very low Q factor. Therefore, it is important that the anode is connected to the LC-tank, and the cathode is used as control input.

An LC-VCO generally consists of an LC tank and a circuit that generates a negative conductance for compensating the losses in the LC tank. The following equation has to be fulfilled to achieve oscillation start-up conditions:

where:

Gm = the negative conductance of the LC tank and

Rp = the equivalent parallel resistance of the LC tank.


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Reader Comments

Equ 2 should read ...(f0/(2*Qtank*Delta*f))^2

rbsingh -February 03, 2006   (Article Rating: )

Sir It is really helpful Thanks a lot Regards SURESH K

Suresh K -January 23, 2006   (Article Rating: )

The creation of a VCO behavioural model and its simulation testbench can be less than intuitive to discrete device level designers; however if you are prepared to expend a minimal amount of effort, you might like to use the techniques illustrated in the following article:

http://www.silicondevices.com/Resources/AppsNotes/ModellingVCOs.html

SimonH -December 20, 2005   (Article Rating: )

i found top20 articles that's nice; but i d't found any ciruit idea section in your site. do u have any idea for the url link where i found these things. if u had plse send me on my E-mail- dlphsharma@yahoo.com

thanking u ravi

Anonymous -December 20, 2005

hello dear sir i'm student in thesis part, my thesis about "design fll" . i try to implement the 100 Mhz LC CMOS vco by circuit maker but i can't get any oscillation . If you can tell me how i can doing the model for mos transistor and diode varactor . if you have practical example please help me. thank you Juan Lee

juan lee -December 15, 2005   (Article Rating: )

hello dear sir i'm graduate student in thesis part, my thesis about "design & simulation cmos pll " . i try to implement the 2.4GHz LC CMOS vco by pspice program but i can't get any oscillation . If you can tell me how i can doing the model for mos transistor and diode varactor . if you have practical example please help me. i'll be very grateful if you kindly help me in this matter.

thank you best regards

E. Hassan

ezzidin -December 07, 2005

i would like to visit here.

allen4583 -November 30, 2005

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Anonymous -November 10, 2005

i need support to design circuit for my thesis, help me. thank's you verry much

danghung -October 09, 2005   (Article Rating: )

i need support to design circuit for my thesis, help me. thank's you verry much

danghung -October 09, 2005   (Article Rating: )

eqn 2 is not correct

Anonymous -May 06, 2005

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