Direct-digital synthesis (DDS) has long promised precise, agile control of output waveforms, although limited in frequency and often in spurious performance. The AD9956 AgileRF^TM DDS from Analog Devices, Inc. (Norwood, MA), however, brings the benefits of DDS technology to an output range reaching 2.7 GHz, providing RF/microwave designers with a high-resolution, programmable signal source capable of sub-Hertz frequency resolution and microscopic current consumption. The high-speed DDS features 48-b tuning resolution, an on-board low-power 14-b digital-to-analog converter (DAC), and flexible, reconfigurable circuitry that can be used for both microwave and high-speed clock generation.

The highly integrated AD9956 incorporates a DDS core, RF divider, DAC, phase detector/charge pump, and differential clock driver (Fig. 1). The design features a 48-b phase accumulator for precise tuning, a 14-b phase offset word to give designers a mechanism of matching system delays, and a 24-b frequency accumulator to provide a method of linearly sweeping between two frequencies. The instantaneous value stored in the phase accumulator represents the instantaneous phase of a sinusoidal frequency. On each system clock cycle the phase accumulator increments by a quantity determined by a value—the frequency-tuning word (FTW)—stored in a control register. The accumulator continues to advance its output value by the FTW until it overflows (i.e., surpasses its maximum value or capacity). A large FTW results in more-frequent overflows, thereby representing a higher frequency. In contrast, a small FTW leads to less-frequency overflows and represents a lower frequency.

The AD9956, with a 48-b phase accumulator, synthesizes a frequency, f₀, according to f₀ = (Tf_s)/2⁴⁸, where f_s is the system clock frequency, T is the value of the FTW, and 0 ≤ T ≤ 2⁴⁷. Any change in the FTW value results in a nearly instantaneous, phase-continuous change in the output frequency. In addition to the 48-b of frequency tuning resolution, a 14-b phase offset register controls the phase of the output in increments of 0.22 deg. The accumulator output increases linearly and cannot directly represent a sinusoidal frequency. As the phase accumulates, the phase-to-amplitude conversion circuit converts the accumulated phase to a 19-b representation of the amplitude of the sinusoid. Following the phase-to-amplitude conversion, the data passes to the DAC for conversion to an analog signal.

Obviously, the 14-b DAC cannot resolve all 48 b of the AD9956's phase accumulator's resolution. Furthermore, converting all 48 b of phase resolution to amplitude information would require a massive, power-hungry digital design. To minimize power consumption and die area, the AD9956 makes use of a subset of the 48-b phase accumulator by only taking the 19 most significant bits (MSBs) and truncating the remaining 29 b before going through the phase-to-amplitude conversion block. The truncation process produces repetitive errors in the digital signal which can show up as spurious content in the output spectrum. However, since the errors are algorithmic in nature, their placement and size are predictable. The magnitude depends on the capacity of the phase accumulator and the number of bits that are truncated. The DAC does not use most of the information contained in the least significant bits (LSBs) of the 48-b accumulator and so truncation generally does not adversely impact performance. The 14-b DAC limits the AD9956's overall spurious-free dynamic range (SFDR), and the spurious contributions are not noticeable if after truncation enough phase information remains to keep their energy below the DAC harmonics.

The AD9956 can also execute multichip synchronization and perform linear frequency sweeps thanks to its 24-b frequency accumulator. By programming start and stop frequencies into the AD9956 along with a step size (the delta FTW), the device can be made to ramp from start to stop frequencies in a linear fashion. The process is controlled externally by changing the state of the PS<0> pin from low to high. Clock generation represents one potential application of the AD9956, so a clock output that coincides with its system clock has been provided to help designers synchronize its signal to other devices in their systems.

The reduced power DDS architecture of the AD9956 includes an important new feature with the addition of an RF divider at the clock input pins. The user applies a reference clock for the DDS and DAC at this divider port. Differential inputs are provided and are internally biased for ease of use. The input reference is the supply rail and provides a 1 V common-mode input range. A simple arrangement would require only AC coupling and the application of a reference clock source. Maximum input frequencies to 2.7 GHz are possible as the divider will bring the reference clock down to the DAC and DDS sample clock rate. The usable system clock frequencies fall in the range of 1 to 400 MHz. The RF divider is a programmable 3-b modulus-2 divider capable of dividing the input 2, 4, or 8 times, generating a low-phase-noise system clock for the chip. The AD9956's integrated DAC provides a 10-mA full-scale current and drives the analog output to about 500-mV pp differential signal when terminated with 25-(omega) resistors. Highlights of the DAC include low power consumption, a 400 MSamples/s update rate, and 14-b resolution. A 1.8-V supply sets the DAC power consumption at 30 mW even while converting data at a 400 MSamples/s rate. The phase noise level is about −125 dBc/Hz offset 1 kHz from the carrier and reaches a noise floor of about −145 dBc/Hz offset 1 MHz from the carrier.