Analog signals once dominated high-frequency designs, such as receivers. But with the growing availability of high-speed analog-to-digital converters (ADCs), with impressive capabilities in translating analog signals to the digital realm, an increasing amount of signal processing is being done by digital hardware. ADCs are currently available from a wide range of suppliers, in numerous formats include as chips, as plug-in circuit cards, and as printed-circuit-board (PCB) assemblies.

ADCs can be readily differentiated by a handful of basic performance specifications, including bit resolution, input bandwidth, sampling rate, bit linearity, power consumption, noise performance, and output types. In operation, ADCs generate a digital code for a discrete value of input voltage. The number of codes is simply 2^N where N = the bit resolution of the ADC. An 8-b device, for example, uses 2⁸ or 256 different digital codes to represent an analog waveform. Although high-performance digital-audio applications have standardized on the use of 24-b converters at sampling rates as high as 192 kSamples/s (kHz), RF and microwave applications generally rely on ADCs with anywhere from 6 to 14 b resolution. (For those wishing a thorough introduction to ADCs, the 69-page "ABCs of ADCs," written by Nicholas Gray, Staff Applications Engineer for the Data Conversion Systems of National Semiconductor, is available for free download from National's website at www.national.com.)

The number, N, of digital bits is directly related to the ADC's signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR). For an ADC, the dynamic range is the ratio of the largest resolvable signal to the smallest resolvable signal. For an ideal ADC it is 6.02N, or about 48 dB for a 8-b ADC. Thus, while it is desirable to have as many bits of resolution for a given application, a general trade-off for ADCs is decreasing bits for increasing bandwidth. Several suppliers, for example, offer ADCs with 1 GHz or greater input bandwidths, although the bit resolution is generally 8 b or less. Nyquist theory is a reliable guide when specifying an ADC for an application. According to Nyquist's criteria, an analog signal with a given bandwidth must be sampled with a sampling rate of at least two times that bandwidth to avoid loss of information. If sampling occurs at a rate of less than two times the bandwidth, a phenomenon known as aliasing of the analog signal will occur resulting in distortion of the analog waveforms. Even when the bandwidth of an ADC is properly matched to an application, aliasing can occur from an excessively wide bandwidth filter preceding the ADC that allows broadband noise to pass into the ADC and/or signal harmonics which the ADC attempts to digitize.

It should be noted that, due to noise and bandwidth limitations, the effective number of bits (ENOB) is a specification often quoted by ADC manufacturers to represent a practical limit for the bit resolution of their devices. Ideally, an 8-b ADC would deliver all 8 b of resolution. Practical considerations, however, typically reduce an ideal 8-b ADC to an ENOB of 7.5 b.

For an integrated-circuit (IC) ADC, the analog input bandwidth is generally set by an on-board track-and-hold (T/H) amplifier preceding the quantizer circuitry. The MAX108 single-channel ADC from Maxim Integrated Products (Sunnyvale, CA), for example, is a 8-b device with sampling rate of 1.5 GSamples/s. It features an integrated T/H amplifier with 2.2-GHz full-power bandwidth and an on-chip +2.5-V precision bandgap voltage reference. The device achieves a near-ideal SNR of 46.8 dB and SFDR of −54 dBc. Designed for supply voltage of ±5 VDC, the ADC handles input signals over a range of ±250 mV. The accuracy of the component can be summarized in terms of its integral-nonlinearity (INL) and differential-nonlinearity (DNL) performance levels, which generally refer to the accuracy of an ADC's overall analog-to-digital transfer function and the accuracy of the step sizes in the ADC, respectively. Measured in terms of a range of an ADC's least-significant bit (LSB)—the smallest digital "slice" of the analog signal—the INL and DNL specifications are generally less than ±1 LSB to avoid ambiguities in the ADC's output data. In some cases, manufacturers will note "no missing codes" on their ADC data sheets to assure engineers that all digital codes are used. For the MAX108, the INL is ±0.25 LSB while the DNL is also ±0.25 LSB. The MAX108 is supplied in a 192-contact enhanced super ball-grid-array (ESBGA) housing. Lower-speed, pin-compatible versions of the device are also available, including the 1-GSamples/s model MAX104 and the 600-MSamples/s model MAX106.