Limiters protect wireless receiver front-ends from irreversible damage due to signal overload. By combining Schottky and PIN diodes in a hybrid limiter design that can be mounted in a compact SOT- 323 surface-mount package, it has been possible to develop a low-cost limiter with 1 dB or less insertion loss from 10 MHz to 1.7 GHz with an input-power turn-on threshold (PTH) of only +2 dBm at 450 MHz. To the author’s knowledge, this is the first commercially available mixed diode technology limiter in a plastic over lead-frame package.

Two common environmental conditions necessitate attenuating signal levels at a receiver’s input¹:
1. Sharing of sites or towers by multiple transceivers subjects a receiver’s front-end stage to overloading from nonsynchronous transmissions (i.e., from other transceivers) via mutual coupling between adjacent aerials. A limiter placed ahead of the receiver’s sensitive low-noise amplifier (LNA) stage prevents overloading when a nearby wireless system transmits. At the end of the nonsynchronous transmission, the limiter rapidly turns off to allow weak distant but desired transmissions to pass unimpeded to the receiver.

2. The circulator or switch that performs duplexing within a timedivision- duplex (TDD) transceiver is limited in isolation performance. A TDD WiMAX transceiver operating in the 2.5-to-3.5-GHz range is an example of a system architecture that requires a limiter in the receive path because of size-constrained circulators or the inadequate isolation of the on-chip switches’ isolation at microwave frequencies. Due to similar transmit and receive frequency, the receiver cannot be protected from the leaked transmit power by means of a pre-LNA filter.

Because of the trend in reduced transistor size for improved gain and noise figure, a wireless receiver’s LNA is particularly susceptible to damage from overloads (Table 1). An LNA’s maximum input power (P_iMAX) rating is usually not dictated by catastrophic failure modes, such as fusing of the bond wires and metallization or meltdown of the transistor junction; both will result in a dramatic reduction in the receiver sensitivity. In the case of a field-effect transistor (FET), rectification of the RF input signal can significantly increase the gate current (I_g) above the quiescent value.² Metal migration, one of the primary failure mechanisms in gallium arsenide (GaAs) and silicon semiconductors,³ is related to the DC current level.⁴ Therefore, exposure to RF input power greater the specified P_iMAX, even if only marginally, potentially shortens component lifetime. Additionally, FETs driven by large RF signals may also exhibit time-dependent degradations in output power⁵ and third-order output intercept point.⁶

The most common limiter configuration is a shunt-connected PIN diode that biases itself in the presence of large signals (a self-biasing PIN diode limiter). Its appeal lies in its minimal parts count; i.e., the PIN diode performs the dual functions of rectifying the incoming RF signal and then using the rectified current to bias itself to low values of effective series resistance (R_d). An inductor completes the loop for the bias current flow while presenting a highimpedance path to RF signals. Choosing a PIN diode with an extremely thin intrinsic (I) layer lowers the input power required to initiate limiting because the thinnest PIN diode has the lowest R_d at a given bias current. Since the height of the I layer is not usually specified in the manufacturer’s datasheet or product specifications, the carrier lifetime (τ) can be used as an estimate of I layer height; i.e., the shortest value of τ corresponds to the thinnest I layer. A self-biased PIN diode limiter based on a thin-I-layer model HSMP-4820 PIN diode from Avago Technologies typically begins limiting at an input level of around +11 dBm.^11,12 Unfortunately, this power level already exceeds the PiMAX ratings of many small-geometry LNA transistors (see Table 1^7-10). Additionally, since wideband inductors are not commercially available in a wire-bondable form, self-biasing PIN limiters are not designed for SOT-323 packaging.

A simple modification that can lower the limiting threshold, P_th, is to use a Schottky diode to generate the bias current for the PIN diode. Since a Schottky diode has a lower turn-on threshold voltage than a PIN diode, a hybrid PIN-Schottky limiter’s P_th is 10 dB lower than a PIN-only limiter. Due to the absence of a uniform naming convention for limiter topologies, the anti-parallel PIN-Schottky diode limiter has been given different names in the technical literature, including the “Schottky enhanced PIN limiter¹³,” the “quasi-active limiter¹⁴,” or the “detector-driven limiter^.15”

The primary aim of creating this multichip limiter in a package is to eliminate the effort and time needed to select the correct diodes when designing limiters. There is a confusingly large variety of PIN and Schottky diode types; each type with its own set of characteristics and performance tradeoffs and this forces the designers to be familiar with PIN and Schottky diode parameters (Table 2^{12, 16, 17}). The secondary goal is to reduce the limiter’s part count and printed-circuit- board (PCB) footprint by combining Schottky and PIN diode chips in a compact industry-standard SOT- 323 package. The power-handling capability of the packaged limiter is maximized because one junction of the diodes makes direct electrical and thermal contact to a copper leadframe resulting in a junction-to-case thermal resistance, Θ_jc of +150°C/W.

The Schottky diode rectifies the incoming RF and produces a current (I_F) that is proportionate to the incident RF power (P_i). The PIN diode, which is connected in an anti-parallel configuration to the Schottky diode, provides a return path for IF. The PIN diode behaves like a currentcontrolled resistor with an equivalent junction resistance (R_d) which is controlled by I_F:

R_d = W²/2µI_Fτ

where

W = the PIN diode’s I layer height,
µ = the ambipolar mobility of the
electrons and holes, and
τ = the minority carrier lifetime.

At power levels below the Schottky detection threshold, the unbiased PIN diode’s Rd is considerably higher than the transmission-line characteristic impedance (Z₀). Therefore, most of the incident power will pass through the limiter with almost no attenuation (A). Above the Schottky detector’s threshold, the rectification of RF produces a current that lowers the PIN diode R_d. The limiter’s corresponding attenuation is given by

A (dB) = 20log[1 + (Z₀/2R_d)]

At very low values of R_d, most of the incident power is reflected back to the source (e.g., the aerial or antenna) and only a small fraction is dissipated in the PIN diode. As a result, the limiter can handle P_i values that are much larger than the PIN diode’s rated maximum power.¹²

Due to the PIN diode’s R_d α W² relationship as mentioned earlier, it is desirable to have a very thin I region–typically, in the 1-to-7-µm range^{12, 19} as the resulting low Rd permits the limiter to turn on “earlier” (i.e., lowers the turn-on threshold, P_th) and to attenuate large signals by a greater amount.

Different Schottky diode construction approaches result in tradeoffs in either the peak inverse voltage (PIV) rating or the zero-bias junction capacitance (Cj0).²⁰ The PIV imposes a limit on the maximum signal amplitude that can be handled by the limiter without damaging the Schottky diode, whereas Cj0 determines both small-signal insertion loss and detection sensitivity. A hybrid silicon Schottky diode was chosen based on its set of performance compromises (Cj0 = 0.5 pF and PIV = 15 V).

The hybrid limiter for evaluation was assembled on a PCB consisting of coplanar-waveguide circuitry with ground plane (CPWG)²¹ on 0.8-mm-thick FR-4 dielectric substrate material. The CPWG trace was dimensioned for a characteristic impedance of 50 Ω using calculations from a free RF design program, AppCAD.²² The CPWG trace length from one edge to the opposite edge of the PCB is 25.4 mm (1 in.). The RF connection to the limiter was made via edge-launched SMA-to-PCB transitions (Johnson 142-0701-841 connectors) soldered at both ends of the CPWG trace. The HSML-5822 PIN-Schottky limiter device was soldered at the approximate center of the CPWG length since mounting it at this position allows the evaluation board to be conveniently modeled as symmetrical halves, simplifying the simulation. The SMA connector nearest to the PIN diode is chosen as the input port, so that the PIN diode can protect the more fragile Schottky diode from high incident Pi.

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