Receiver front ends for mobile television must provide the sensitivity needed to operate at far distances from a transmitter, but must provide overload tolerance when in the presence of large signals. Mobile television receive capability, which will be integrated into a large number of portable electronic devices, including cellular handsets, portable digital assistants (PDAs), laptop computers, and in-car-entertainment (ICE) systems,^1,2 must provide good performance even as a user’s distance between the transmitter and receiver changes with travel, unlike traditional broadcast television. A low-cost solution to achieving high front-end mobile television receiver sensitivity with overload protection combines a high-gain lownoise amplifier (LNA) with a PIN diode bypass switch.

Most practical approaches to implementing mobile television receivers rely on reducing receiver gain in the presence of large signals. Varying RF signal gain eases the linearity requirements for the mixer stage3, allowing the use of low-cost radio-frequency integrated circuits (RFICs) to create the receiver module. In the cascade analysis of a receiver front end with switchable or adjustable gain (Fig. 1, Table 1), the input third-order intercept (IIP3) improves as a function of the gain change. A receiver with adjustable gain handles large signals better than a receiver with fixed gain.

Automatic-gain-control (AGC) circuitry is also used to vary LNA gain,^4,5 and because it is typically implemented prior to the channel filters, it can respond to overloads from adjacent-channel transmissions.

One way to reduce RF gain is to shunt part of the RF signal to ground prior to the LNA [Fig. 2(a)]. This approach uses a minimal number of RF switch elements but, when the switch is closed, causes an impedance mismatch that can affect other portions of the system. A variation involves connecting the damping element to the high-impedance or “hot” end of the LNA’s parallel resonant network, although this sacrifices RF selectivity prior to the LNA for the sake of a larger gain-control range.⁶

Alternately, it is possible to bypass the LNA stage with a pair of RF switches when a received signal overloads stages following the LNA, such as a mixer or intermediate-frequency (IF) amplifier. During bypass operation, input signals are directly routed to the frequency downconverter IC [Fig. 2(b)]. As long as the components in the bypass signal path are matched to the characteristic impedance (75 Ohms in mobile television), mismatches will be minimized. Of course, adding the switches also adds to the circuit complexity.

In yet another approach, RF gain is lowered by decreasing the quiescent current to the LNA’s active device [Fig. 2(c)].^7,8 Amplifiers and devices based on this technique, such as dual-gate MOSFETs, use additional device terminals for controlling the bias current. This gain-control method has the lowest circuit complexity since switching elements are not used, but suffers from degraded linearity as the collector/drain current is reduced below the nominal device DC operating point.⁹

To meet a customer’s requirements (Table 2) for an LNA for a dual-mode (analog/ digital) mobile television receiver in the 47-to-870-MHz range, several MMIC options were considered, but disregarded for their inadequate linearity. Using a wideband high-linearity MMIC LNA (model MGA-68563) and an external PIN diode switch, a solution was developed.

The single-stage GaAs pHEMT LNA uses devices with gate width of 800 microns (Fig. 3). The device gate is connected to an internal current mirror to compensate for process variations and to minimize the effects of threshold voltage variations. The LNA employs lossy negative feedback for stability and to flatten the amplitude response within a 3-dB window from 100 MHz to 1 GHz.¹⁰

With its internal feedback and better than 10 dB output return loss, the MMIC didn’t require output impedance matching. But matching the input of the MMIC for such a broad frequency range (47 to 870 MHz) proved difficult and required an unconventional approach in which the FET drain current, I_ds, is varied above the nominal 10-mA value to optimize the input return loss. The required input return loss performance was met with 20 mA Ids, but a value of 30 mA was chosen to allow enough margin for any degradation by the addition of the PIN diode switching circuit. Pin 4 on the MMIC LNA controls the current flow through the internal bias generator via external resistor R1 [Figs. 3(a) and 4(b)]; altering the dimensions of R1 changes I_ds while the supply voltage V_d remains fixed at 3 V. The 300-percent increase in nominal Ids provides higher linearity.

In designing the LNA/switch circuit, the first iteration required four PIN diodes for the bypass switch [Fig. 5(a)]. It is a common configuration for a double-pole, double-throw (DPDT) switch. The circuit operates by turning on the upper pair of PIN diodes while the lower pair is zero biased, and vice versa. During normal operation, only the lower PIN diode pair is turned on and the RF signal is amplified by the LNA. When RF gain must be reduced, the upper PIN diode pair is turned on and the RF signal is routed around the LNA in bypass mode. The resistors are used to regulate the PIN diodes’ forward current and to isolate RF signals from the logic control ports V_SW1 and V_SW2. This first iteration required a high component count, so a simpler solution was sought.

Working with customer feedback, a simpler double-pole, single-throw (DPST) switch arrangement was developed [Fig 5(b)] in which only the bypass path is connected or disconnected from the input and output ports. Because the LNA path is no longer switched in or out, the LNA supply (V_dd) must be turned off during bypass mode to make use of the intrinsic isolation of an unbiased FET. This approach degrades the return loss of the bypass path, due to this path having the shunt finite gate and drain impedances of the unbiased FET.

In normal operation, the supply to the PIN diodes is turned off (V_SW = 0 V) and the supply to the LNA is restored to 3 V. But these zero-biased PIN diodes suffer some parasitic capacitance that allows higher frequencies to pass. As a result, the LNA gain and return loss are degraded by incomplete isolation of the bypass path from the input and output ports.

In the LNA/switch, inductors L1 and L2 are ferrite beads that present high impedances over the full range of the biasing networks for the MMIC and diodes [Fig. 5(b)]. Without L1 as a choke, part of the input signal will be shunted to ground via resistor R3’s parallel-connected parasitic capacitance. ¹¹ Measurements made on a prototype without L1 verify that the inductor prevents degradation in the LNA’s noise figure. Capacitors C3, C4, and C5 decouple RF signals from the DC supply and are sized for low reactance (X _c 5 Ohms at the lowest operating frequency. Capacitors C1 and C2 provide DC blocking at the MMIC input and output. A small value is deliberately chosen for C2 to create a highpass response that can compensate for the MMIC’s intrinsic gain rolloff at high frequencies. Resistors R1 and R2 control the MMIC supply current and are sized for 30 mA at a V_dd of 3 V. Resistors R3, R4, and R5 limit the PIN diodes’ forward bias to about 2.5 mA per diode at V_SW of 3 V. [Please contact the author for a component value list for Fig. 5(b).]

The circuit could be further simplified by using only one PIN diode. There is no advantage in this, however, since a diode pair occupies the same SOT-23 or SOT-323 surfacemount package as a single diode, with negligible price difference. The pair of diodes also offers some advantages: the series connection cuts in half the parasitic capacitance and, since the even-order harmonics generated by the anti-series pair of PIN diodes are out of phase, they will cancel.¹²

Continue to next page.