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[Communications]
Semiconductors Simplify Direct-Conversion Design
Advances in semiconductor processes have enabled integrated circuits with the performance needed for wireless infrastructure direct-conversion receivers for multimode communications systems.

Cecile Masse  |  ED Online ID #22471 |  March 2010
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Direct-conversion architectures enable the broadband radios needed to support multimode, multiple standards in third-generation (3G) and fourth-generation (4G) wireless networks. The capability of handling signals from 400 MHz to 4 GHz across the globe has pushed infrastructure and mobile-device developers to seek new levels of performance for the components in those systems. Fortunately, improved silicon germanium (SiGe) and CMOS semiconductor processes are allowing higher levels of integration with low power consumption. And a direct-conversion architecture enables a radio designer to cover a large frequency range and with scalable bandwidths on a single hardware platform. It offers many advantages over traditional IF-sampling receiver approaches for wireless base stations, and combined the benefits of a balanced and blocker-immune RF demodulator with analog-to-digital converter (ADC) technology utilizing adaptive correction techniques for the residual signal impairments.

The 3G Long Term Evolution (LTE) wireless communications standard supports a variety of channel bandwidths from 1.4 to 20 MHz. A minimum bandwidth requirement of 20 MHz is commonly used, whether the equipment supports LTE-only carriers or a mix of 3G (WCDMA) or LTE (OFDM) carriers. Such wide bandwidth allows multiple adjacent or nonadjacent carriers to be received. For example, as many as four adjacent WCDMA signals can crowd a 20-MHz bandwidth.

The challenges of a broadband receiver design lie in the capability to demodulate low-level, high-datarate signals in the presence of high interfering signals. By definition, a multicarrier RF receiver has no analog channel selectivity, and unwanted blockers reach the ADC without being attenuated. This leads to high dynamic-range requirements for the receiver building blocks, especially the ADC. For instance, a 3G LTE blocking requirement calls out narrowband blockers 60 dB above the desired signal. As a result, a multicarrier receiver should have a high input 1-dB compression point, high-resolution ADCs, and some form of automatic gain control (AGC) to maintain blocker signal levels below the full-scale (FS) level of the ADC.

This immunity to blockers must be achieved along with acceptable receiver sensitivity. A base-station receiver designed to support the 3G LTE standard must have a noise figure (NF) of better than 5 dB. To reach this level of performance with margin, the downconverting mixer or demodulator is typically preceded by a few low-noise-amplifier (LNA) stages. Front-end gain helps improve the overall NF according to the Friis equation:

NFtotal = NFLNAs + (NFdemod - 1)/ GLNAs+[NFADC -1/(GLNAsGdemod)] (1) However, front-end gain cannot be set arbitrarily high since a strong blocking signal at the antenna could bandcause receiver saturation. Also, excessive gain can degrade linearity and affect signal integrity when intermodulation products from high-level blockers fall within the desired signal bandwidth. A suitable quadrature demodulator must provide a good balance between noise figure and linearity, as measured by the third-order intercept point (IP3).

Quadrature demodulator amplitude and phase errors can cause inband images or unwanted sideband energy. In a multicarrier receiver, strong in-band interfering signals may be adjacent to modulated carriers at the receiver sensitivity level. Maintaining adequate amplitude and phase balance through the baseband demodulation process is critical to good receiver performance. The image-rejection requirement is determined by the difference between the strongest and weakest in-band signals, the required signal-to-noise ratio (Eb/No) for demodulation, and margin for other noise contributions. The 3G LTE standard calls for at least 60-dB total image rejection. Reciprocal mixing in a broadband receiver is also an important phenomenon to consider when specifying demodulator localoscillator (LO) phase noise. The LO phase noise modulates nearby unfiltered blockers, adding Pblocker_dBm - LO_Noise dBc/Hz noise to the wanted channel.

A direct-conversion signal chain (Fig. 1) provides a low-cost receiver solution for 3G and 4G systems. It is a less complex architecture than other receivers, not requiring the multiple surface-acousticwave (SAW) and discrete filters used in a real IF sampling architecture. The baseband channel filter is typically a discrete lowpass design that provides both out-of-band blockers and broadband noise rejection before digitization. It can be designed with much lower insertion loss and cost than the IF filters used in super-heterodyne or real- IF sampling architectures. With an I/Q demodulator, the baseband cutoff frequency need only to be one-half of the total signal bandwidth for a complex modulated signal centered at 0 Hz.

For example, assume the multicarrier RF input signal at the receiver antenna is a nonsymmetrical doublesideband signal centered on a carrier frequency F0. A quadrature demodulator operating at LO = F0 converts the real RF signal into a complex baseband signal. It generates both the real and imaginary components at the difference and sum frequencies LO+/- F0 or 0 Hz and 2F0. Lowpass filters remove the sum terms, signal harmonics, and noise before analog-to-digital conversion. If the total signal bandwidth is Bx, then the filter cutoff frequency should be set at Fc> Bx/2.

Another key advantage of a directconversion approach is the lower ADC sampling rate requirement since the I/Q signal bandwidth is only onehalf the total composite signal bandwidth. With downconverted signals centered at DC, the sampling theory then requires a sampling rate at least 2(Bx/2) or Bx, which is one-half of the minimum sampling rate required by an IF sampling receiver for the demodulation of the same bandwidth. For a 20-MHz-capable LTE receiver, this corresponds to a Nyquist sampling rate over 20 MHz for each I and Q path (Fig. 2).

Despite the advantages, directconversion radio design does not come without difficulty. Any gain or phase imbalance on the I and Q paths or non-exact 90-deg. phase shift of the demodulator circuit will result in energy at the unwanted sideband frequency. When such a receiver downconverts the desired multicarrier signals around zero Hz (zero-IF), the desired carriers will be on both sides of DC (Fig. 3). Carrier 1 image around DC appears on the next channel where a weaker carrier may be present. Poor image rejection will therefore limit the receiver sensitivity if no digital calibration is used. Anti-alias filter components tolerance may also impact the overall image rejection performance. Until recently, it was quite difficult to achieve acceptable levels of gain and phase balance over a wide bandwidth. Newer SiGe process technologies enable high-quality RF performance to 6 GHz for the demodulator’s active mixer cells.

In the baseband down-conversion process, some energy is generated at DC through the quadrature modulator. Any LO signal leaking back to the RF input mixes with that same LO signal, resulting in a DC component. Demodulating the RF carriers to a multiple of one-half of the channel bandwidth is one way of avoiding co-channel DC offsets. The DC component amplitude should not impair the receiver’s ability to receive weak signals.

As part of a direct-conversion receiver, the ADL5380 and ADL5382 I/Q demodulators from Analog Devices were designed to achieve broadband operation with optimum LO leakage and image suppression. Ideally, the demodulator implements a single-sideband mixing operation with two mixers. An amplified local oscillator (LO) signal is fed directly to the first mixer, while that same signal, shifted by 90 deg., is fed to the second mixer.

To meet the performance specifications with sufficient margin, the I/Q demodulator employs an optimized LO buffer and phase-shifter circuit. Its innovative circuit topology maintains an accurate 90-deg. phase shift over a wide frequency range, while maintaining circuit noise below the phase noise from the LO PLL. The design is optimized for minimum AM/PM distortion, making it insensitive to LO drive level with enhanced secondorder distortion performance.

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