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[Components]
Image-Reject Mixer Arms Direct-Conversion Receivers
With biasing techniques such as those used for power amplifiers, an image-reject mixer fabricated with a standard CMOS process can deliver improved linearity.

J.G. Gardiner, Nandi Logan, J.M. Noras  |  ED Online ID #22469 |  March 2010

Mixer linearity is critical to the performance of direct-conversion receivers with low intermediate frequencies (IFs). By biasing a low-IF image-reject mixer designed for a fully duplex system, such as UMTS, it is possible to achieve outstanding linearity even in the presence of large blocking (interference) signals, and even in a UMTS system, where the transmit signal is often the largest blocking signal for the receiver. The mixer is designed for bias in the Class AB region and is meant for use with a highly linear low-noise amplifier (LNA).

The image-reject mixer (Fig. 1) consists of eight switching transistors and four transconductors, with the IF at 100 MHz rather than at DC (0 Hz). It directly downconverts a received signal to a low IF using fewer parts and local oscillator (LO) stages. The image reject direct-conversion method has the added advantage of requiring fewer filtering components.

However, these advantages are somehow mitigated by the added problems of a receiver more prone to flicker (1/f) noise, the challenge of achieving good DC rejection, and linearity issues with high second-order and third-order intermodulation products.

The second-order products, characterized by the second-order intercept point (IP2), can be a particular problem in direct-conversion receivers1 since the second-order nonlinearity also demodulates the amplitudemodulation (AM) component of the amplitude-modulated blocker down to baseband, reducing the receiver’s blocking margin. In addition, due to the possible presence of closely spaced interferers, the downconverter also requires a high IIP2.

Due to the reduced amount of filtering, a direct-conversion receiver is more sensitive to intermodulation products, requiring a down-converter mixer with high input third-order intercept point (IIP3). Although the IIP3 can be improved by adjusting bias levels and device size, IIP2 improvements are typically achieved by improving the symmetry of the design, improving the quality of the LO signal, and improving the LO-to-RF port isolation of the mixer. Low-IF receivers must deal with LO feedthrough, with RF and LO signals at similar frequencies. Although direct interference of LO with RF is not an issue in a low- IF receiver, LO phase noise and phase stability can impact how an incoming RF signal is processed. To avoid this, the LO is usually operated at twice the required frequency and then divided by two.

Since enhancement-mode CMOS transistors are essentially surface devices, they exhibit far more 1/f noise offset through about 100 MHz than devices fabricated with other semiconductor processes, due to the phenomenon of charge trapping. This can impact system noise figure since it adds FM noise that in return restricts the data that can be received by the discriminator circuit.

The image-reject mixer is a quadrature Gilbert-type direct-conversion mixer (Fig. 2). It consists of eight switching transistors (M5 to M12) and four transconductors (M1 to M4), arranged in symmetry. A pair of switching transistors and a single transconductor constitutes a single-balanced mixer. Each of the differential inputs to the mixer has a transconductor stage based on a single NMOS device. The transconductor converts available voltage to current to be mixed by the upper section of the switches, operated at the LO frequency. The upper switching section is controlled both by a gate bias and by the LO signal at its input. The applied gate bias thus acts as an offset voltage to the mixing action of the circuit. Sharp transitions in the LO signal reduce the zero-crossing noise contribution and nonlinearity.

Flicker nose is contributed by two mechanisms2: the zero crossing of the tail current (the direct method) and the induced current in the tail capacitance (the indirect method). Larger capacitive gates tend to reduce the flicker noise as they filter out some of the noise.3 The width of the transistor has been set to 1.5 mm, which is rounded from the recommended width of 1.54 mm for optimum FT.

The minimum noise figure is illustrated in Eq. 1 4.

where

? = the body coefficient,
d = the gate noise coefficient, and
c = the correlation coefficient.

Due to the frequency-conversion requirements when working at low IFs, the use of reactive components is not feasible and active loads result in excessive noise. Because of this resistive loads are used, although they add to voltage consumption. The specifications for the image-reject mixer were derived from the overall specifications for the UMTS receiver as well as the LNA’s design specifications. Given that the 3GPP5 UMTS standard specifies a maximum of -43 dBm at the receiver input for high gain selection, this then provides the values shown in Table 1. It includes a listing for the maximum signal present under typical conditions at the input of a receive demodulator mixer. But because the system is full duplex, and the transmit signal can also be present at the receiver’s input, the mixer must be able to handle a relatively high input level under full-duplex conditions (Table 2).

The conversion gain, Gc, of the image-reject mixer can be calculated from Eq. 3 8:

Since voltage gain, AV, is equal to the output voltage divided by input voltage,

If the degeneration resistance, RSource, is approximately equal to zero, then

The optimum transistor width, wopt, is derived from Eq. 68:

from which it can be deduced that the larger the value of input impedance, Rin, the smaller the value of wopt and the lower the Cgs and Cgd capacitances. The lower the junction capacitance, the higher the value of FT. implying a better noise figure.

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