Low-noise-amplifier (LNA) design requires tradeoffs, often among such goals as noise figure, gain, linearity, and stability. In addition, portable applications call for low power consumption. But through the use of a common- gate (CG) architecture for input impedance matching and reduced power consumption through currentreuse techniques, an RF CMOS LNA was developed with 15.5-dB forward gain and 1.68 dB noise figure at 2.4 GHz. With its excellent input and output impedance matching, it consumes only 1.05 mW power.

Low-voltage and current-reuse design approaches can effectively decrease power consumption,^1-9 including the use of cascode amplifier configurations.^1-4 With the currentreuse topology, desirable gain can be achieved with relatively low current consumption. However, due to the use of multiple transistors, it employs increased supply voltage. To lower the supply voltage, a folded topology has been proposed.^5,6 The required supply voltage is reduced by one transistor compared with that of a cascade amplifier. Unfortunately, with more than one gain stage, the total current consumption of a CMOS LNA may not be minimized. A current-reuse, two-stage common-source (CS) topology can provide high gain at low supply voltage and power consumption, although at somewhat elevated noise levels.^7-9 With a current-reuse, two-stage CG topology, however, both high gain and low noise figure can be achieved at low voltages and power consumption.

The inductor-degenerated CS topology is a popular LNA choice for narrowband applications; it provides both high gain and relatively low noise figure. But it provides low noise figure via high power consumption and/or high-quality-factor (high-Q) off-chip inductors. The noise figure of these structures increases sharply as the power consumption is decreased. ¹³ For a low-power receiver, an LNA based on a CG approach is the preferred topology.¹¹ At 2.4 GHz, CG LNAs typically offer lower noise figures than CS LNAs for power consumption below 3.1 mW.¹² Compared to CS LNAs, CG LNAs feature broadband input match and better linearity and stability.¹³ To achieve a low noise figure with low power consumption, a CG LNA input structure was used (Fig. 1); by tuning input inductor LS and capacitor C1, the noise figure can be reduced to minimum. In addition, this structure’s current-reuse two-stage topology provides relatively high gain with reduced power consumption.

In Fig.1, CS MOS transistors M₁ and M₂ represent the first and second stages, respectively, of the LNA. They share the same DC bias current flowing through L₁ to reduce power consumption. The amplified RF signal from M₁ is directed to the gate node of M₂through coupling capacitor C₄. Capacitor C₃ is the RF bypass for M₂. Inductor LS and capacitor C₁ help to obtain simultaneous power and noise matching for the input stage, while output matching is provided by Ld, C₂, and C₅. The LC network L₁-C₄ between the gain stages is used for interstage matching.

The proposed LNA topology is basically a two-stage amplifier (Fig. 2). The overall transconductance is equal to the multiplication of the individual transconductances of devices M₂ and M₂. Therefore, it has a comparable power gain to the cascaded CS amplifier topology.

The input of the LNA must be matched to the output of the filter following the antenna to minimize reflections between the LNA and the antenna. The proposed LNA is treated as a two-stage amplifier, with simplified circuit model in Fig. 2. The conditions for input matching7 are shown in Eqs. 1-3:

where Z_source is the impedance seen at the gate of M₁ when looking toward the antenna,

Zin,1 is the input impedance of M1, and ZL is the load impedance.

A simple, small-signal equivalent circuit of the first gain stage is illustrated in Fig. 3 where RS is the source impedance, and gm represents the transconductance of the MOSFETs. In Fig. 3, the input impedance of M1, Zin, is expressed by Eq. 4:

From Eq. 4, the input impedance matching to a 50-Ohm system can be achieved by

From Eqs. 5 and 6, the operating frequency, ?0, can be derived as

From the input matching conditions described in Eqs. 1-3, the effective transconductance of the first stage, g_M1,eff, can be written as:

(See Eq. 8)

where s = j?₀ and g_M1 is the transconductance of M1. From Eqs. 1-3, it is possible to also know the effective transconductance of the second stage, g_M2,eff, as

where g_M2 is the transconductance of M₂ and C_gs2 is the gate-to-source capacitance of M₂. The overall effective transconductance is equal to the multiplication of the individual transconductance of M₁ and M₂. Therefore, two cascaded stages are employed in the proposed LNA topology to boost the amplifier gain for ultra-low-voltage operation.

As the first active building block in an RF receiver, the LNA is required to provide sufficient gain such that the noise contributed from the following stages can be effectively suppressed. In a cascade amplifier, the total noise figure can be expressed¹⁴ by Eq. 10:

where NF_n and G_n are the noise figure and gain of the nth stage, respectively. According to Eq. 10, the noise figure and gain of the first stage are both very important for total noise figure contribution. Thus, the first stage should be carefully designed to achieve a good input matching and to make a tradeoff among gain, noise figure, and power consumption.

The noise factor of a two-port network, such as the LNA, can be expressed¹ as Eq. 11:

where F_min is the minimum noise factor, Gn is the equivalent noise conductance, Z_source = R_source + jX_source is the impedance seen at the input of the LNA when looking toward the antenna, and Z_opt = R_opt + jX_opt is the optimum source impedance. Although Fmin can be minimized by properly choosing the width of the MOS device, this is not a good choice for constant DC current. To minimize the NF, [where NF=10log(dB)], it is crucial to design the matching network of the LNA such that the second term in Eq. 14 is close to zero, which in turn means that Z_source should be close to Z_opt.

The matching conditions for minimum noise figures of the cascaded gain stages7 are given by Eq. 12:

with the matching conditions specified in Eqs. 1-3 and 12 resulting in

From Eq. 13, this yields

From Fig. 2, the relations of Eqs. 16 and 17 can be found:

According to the definition of a matching network, the noise and power matching of the LNA are achieved when Eqs. 14 and 15 are satisfied. Therefore, when R_opt is larger than R_in,1, there is a tradeoff between the noise figure and S11. Using a CS LNA configuration with inductive degeneration for input matching, power and noise matching cannot be obtained simultaneously at low current bias, thus the noise figure could be potentially high for low-power applications. For a low-power LNA, a CG LNA is the preferred topology.

In the proposed LNA, even when the MOSFET’s R_opt is larger than R_in,1, from Eqs. 16 and 17, it is possible to adjust the sizes of M₁, LS , and C₁ to achieve optimum input matching and noise matching simultaneously. In addition, a value of S₁₁ of less than -10 dB is adequate for an LNA in most applications.¹ Therefore, the value of R_source can be brought much closer to the value of R_opt by altering the values of L_S and C₁ for better noise matching, while S₁₁ is less than -10 dB. Noise figure responses with various values of L_S and C₁ are shown in Figs. 4(a) and 4(b), respectively, indicating that is it possible to reduce the noise figure as low as possible by adjusting the values of L_S and C₁. With shunt capacitance C₁, the value of L_S can be decreased to a level suitable for on-chip integration.

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