Assessing post-production- tuning (PPT) elements should be part of any RF worstcase circuit analysis (WCCA). Unfortunately, PPT elements are often omitted or incorrectly incorporated into an analysis, even though including such tuning elements into a computer-aidedengineering (CAE) model is often a simple task. Correctly accounting for PPT elements depends on the ability to define the PPT procedure and to mathematically define the relationships for the PPT elements within a circuit model. To demonstrate one straightforward approach for incorporating tuning into a CAE simulation model, a simple amplifier circuit will be used as an example.

A simple and very common form of tuning is the parallel tuned inductive-capacitive (LC) network, commonly used as collector loads in Class A amplifiers, oscillators, and other narrowband applications. A simple amplifier circuit is shown in Fig. 1. Tuned output stages like this are often “tuned” or “peaked” to adjust the center frequency of the output bandpass filter, for the purpose of optimizing the performance of the amplifier. It is possible to either tune the inductor or the capacitor as the adjustable element in this circuit. In most applications, it is the capacitor that is tuned; however, the methods and results shown in this article are applicable in either case.

In this simple example, it is assumed that two parameters affected by the tuned output stage are of primary concern: center frequency and quality factor (Q). By inspection, it is apparent that the center frequency is a function of the product of inductor L₁ and capacitor C₁, while Q is a function of (L/C)^1/2. These two parameters were selected for this example since one is the primary function (frequency), which is being tuned, while the other (Q), is an indirectly related function. The Q is not being tuned, but is being affected by the tuning being performed on the primary function.

The two most common methods generally employed to solve such a problem are as follows. The first method is to ignore the tuning altogether. This is a simple case to analyze, and an approach taken all too often. The results from this approach are often disastrous as many circuits cannot meet their intended performance levels without proper tuning. The second common method is to remove the initial tolerance of all components and perform the CAE simulation. The results are generally more accurate than ignoring the tuning for the primary tuned parameter, but are less accurate for the indirectly related parameters. For example, removing the initial tolerances from the simulation will improve the center frequency, which is what is being tuned, however the results will be incorrect and optimistic for Q. It is often the case that tuning to improve one parameter will effectively degrade other related parameters. That is the case here, in that increasing the accuracy of the center frequency will degrade the Q, as will be seen later in this article. This is particularly troubling, since the error is on the beneficial side, providing misleading results because they exceed the correct values. It is generally desirable, at least for the purpose of WCCA, to have errors fall on the conservative side, so that the reported result is worse than the maximum result.

A more correct approach can be shown by implementing it in an amplifier model within the Advanced Design System (ADS) suite of CAE software simulation tools from Agilent Technologies. In the simple example amplifier circuit (Fig. 2), the two elements involved in the tuning are inductor L₁ and capacitor C₁. The tuning method breaks each element in the tuning process into two separate parts. One part is the component, including tolerances to the point that the circuit is tuned. The second part includes the tolerances of the component that occur after tuning takes place. In many cases, the circuit is tuned in a room-temperature environment, so that the “pre-tune” element in ADS will include the nominal value and its associated initial tolerance. The “post-tune” element in ADS will then include the tolerances that occur after tuning. In many cases, this includes temperature tolerances, aging or long-term stability tolerances, and possibly radiation exposure effects. The temperature tolerance is sometimes included in the “pretune” element. This is often the case in oven-controlled crystal oscillators (OCXOs), where tuning occurs at the controlled, oven temperature.

The next step is to create a relationship between the tuning elements. For example, in this simple amplifier example, the frequency of the tuned parameters can be described as:

Freq = 1/2(L₁*C₁)^0.5

If the intention is to tune the circuit to a particular frequency, Freq, then the value of capacitor C₁ can be found as a function of L₁:

C₁ = 1/(2Freq)²L₁

With the capacitor configured as the tuning element, it is possible to determine the initial value of the capacitor as a function of the ADS pretune value of L₁. The capacitor tolerances that occur after tuning are then incorporated into C₁_Post_tune and the inductor tolerances that occur after tuning are then incorporated into L₁_Post_tune.

This relationship, so far, assumes that capacitor C₁ is infinitely adjustable and that any required value can be obtained. In some cases, primarily in commercial applications, this may be feasible through the use of variable capacitors or even varactor diodes. In most military and space applications, however, fixed elements are generally used as tuning elements. In this case, the resolution of the setting and the tolerances of the fixed component also need to be considered. Suppose that the tuning capacitor has a nominal required capacitance of 300 pF.

This is not a standard capacitor value and the nearest standard values would be 270 or 330 pF. In either case, the capacitor is 30 pF or 10 percent from the desired value. In addition, once a standard capacitor is selected, the capacitor also has a tolerance. For example, if a 270-pF, 5-percent capacitor is selected, then, at +25ºC the capacitor could be as low in value as 257 pF or 14.3 percent below the desired value while a 330-pF, 5-percent capacitor could be as high as 347 pF or 15.5 percent above the desired value. This “setting” accuracy is included in the “post-tuned” tolerance of C₁.

Of course the problem becomes more difficult with the addition of parasitic elements, such as the self-resonant frequency (SRF) of the inductor, though the CAE tuning method still applies. The SRF capacitance can be added as an additional capacitor in the model or added to the “pretuned” capacitance, since that element occurs prior to tuning. It is also common to use more than one capacitor to set the tuning. It is common to use two parallel capacitors, one with a large value and one with a small value, in order to improve the tuning resolution.

To demonstrate the tuning method, a simple amplifier circuit can be used as an example (Fig. 3). Tolerances are only applied to the tuning elements in order to keep the example as simple as possible. In this example, the SRF of the inductor, L₀, is ignored and two parallel capacitors are employed in order to improve the tuning resolution using fixed elements. The example parameters consist of a desired frequency of 10 MHz, a desired Q of 10, L₀ = 800 nH, C₀ = 270 pF, and C₁ = 47 pF. The tolerances of inductor L₀ are initially 10 percent, 2 percent with temperature, and 2 percent with aging. The tolerances of capacitors C₀ and C₁ are initially 5 percent, 0.5 percent with temperature, and 1.25 percent with aging.

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