Tweet [Components] Compact PLLs Integrate VCOs This line of low-phase-noise PLL frequency synthesizers includes integrated voltage-controlled oscillators to provide miniature frequency sources for a wide range of high-frequency applications. Hittite Microwave | ED Online ID #22026 | October 2009 Low-noise local oscillators (LOs) are critical to many RF/microwave systems in commercial, industrial, and military applications. Simply put, the higher the performance of the LO, the better the performance of the system in terms of receive signal sensitivity and bit error rate (BER) capability. One of the most common methods of generating a stable LO source is to combine a low-phase-noise voltage-controlled oscillator (VCO) with a stable reference oscillator to form a phase-locked-loop (PLL) frequency synthesizer. Unfortunately, interactions between components within the PLL synthesizer, including the charge pump and loop filter, can offer challenges for the best designers, not to mention issues that arise due to circuitboard layout and power-supply noise. By leveraging expertise in frequency-generation components, however, the engineering team at Hittite Microwave has developed a line of PLLs with integrated VCOs to simplify the development of PLL-based frequency synthesizers. The new product lines include eight PLL/VCO sources covering 665 MHz to 3.7 GHz and four PLL/VCO sources spanning 7.3 to 13.4 GHz. Each of the synthesizers (see table) includes an advanced fractional-N frequency synthesizer and a low-noise VCO and is supplied in an industry-standard 6 x 6 mm QFN plastic package that requires a minimal number of external components to achieve high performance. Figure 1 is a simplified block diagram showing many of the core functions within the PLL with integrated VCO products, and how they may be used to drive the LO port of a typical RF/microwave transceiver. The advanced PLL/synthesizer section was designed for low-phase-noise applications and includes a low-noise phase/frequency detector (PFD), a precision-controlled charge pump, and an advanced modulator design that allows ultrafine frequency steps. The PLL/synthesizer section also provides the ability to alter both the PFD gain and the cycle slipping characteristics of the PFD. The Cycle Slip Prevention (CSP) mode essentially holds the PFD gain at maximum until the frequency difference from the goal is near zero. The CSP mode allows significantly faster lock times and can reduce the time to arrive at a new frequency by 50 percent compared to conventional PFDs. A high-frequency reference path allows the use of reference sources to 220 MHz, while source buffers in the reference path support both square-wave and 50- sinusoidal reference oscillators. Low close-in phase noise and low spurious noise also permit architectures with wider loop bandwidths for faster frequency hopping and low microphonics; spurious outputs are low enough to eliminate the need for costly direct-digital-synthesizer (DDS) references in many applications. For example, model HMC826LP6CE is one of eight PLL/VCOs optimized for RF market applications, and targeted at cellular/4G, WiMAX, and measurement equipment. Each of the eight devices combines the functions of a high-performance fractional-N PLL/synthesizer and fully integrated low-noise VCO. The architecture supports high-performance VCOs with voltage tuning requirements of less than 5 V (Fig. 2). In this topology, an operational amplifier is not required in the loop filter, saving both cost and circuit-board space while improving performance. The devices can be locked at one temperature extreme and then operated over the full temperature range without the need for relocking or recalibration. This capability is required in high reliability applications, but not offered by some competing solutions. As shown in Fig. 3, these devices offer exceptional phase noise performance— typically 10 dB better than competing devices both in-band and at the farout noise floor, all without the need to choose between low spurious or lownoise modes. The typical integrated noise of –55 dBc at offset frequencies from 100 Hz to 1 MHz is equivalent to 0.1 deg. of root-mean-square (RMS) jitter, or 278 fs RMS jitter in the time domain at an output frequency of 1 GHz. The model HMC826LP6CE offers a marked improvement in performance over existing integrated solutions. It has approximately 10 dB lower closein phase noise and 12 dB lower phase noise floor at offset frequencies greater than 20 MHz compared to a commercial alternative. In addition, the HMC826LP6CE offers superior spurious performance with much lower fractional spurious content across the band and a cleaner overall spectral output. The HMC826LP6CE features consistent performance over temperature at the band edges, to ensure no drop-outs at those frequencies. The eight RF models include three PLLs with integrated VCOs that offer multiple outputs based on dividing or multiplying the fundamental (f0) output frequency [divided (f0/2), fundamental (f0), and doubled (2f0)] for added versatility and ease of use in multiband applications. Furthermore, the entire family features a common 6 x 6 mm QFN package footprint and common SPI control protocol. The HMC764LP6CE PLL with integrated VCO is one of four devices optimized for microwave market applications. Typical applications include microwave and millimeter-wave radios, industrial/medical test equipment, military communications, electronic warfare (EW), and electronic countermeasure (ECM) subsystems. As shown in Fig. 4, the model HMC764LP6CE PLL with integrated VCO exhibits consistent tuning sensitivity and high output power to +16 dBm across its bandwidth, making it ideal for driving the LO port of many of Hittite’s high-linearity, double-balanced and in-phase/quadrature (I/Q) mixer and receiver products. Figure 5 shows the outstanding SSB phase-noise performance versus offset frequency for the low-, mid-, and high-frequency ranges of the HMC764LP6CE PLL with integrated VCO. This data was measured with a reference frequency of 50 MHz, a loop bandwidth of 100 kHz, and a comparison frequency of 50 MHz at the PFD. The phase-noise performance is consistent over temperature and mechanical shock due to the monolithic construction. Furthermore, a built-in frequency-shift-keying (FSK) mode allows the device to be used as a simple low-cost direct frequency-modulation (FM) transmitter source. Continue to page 2
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