Scaling silicon CMOS transistors to smaller and smaller dimensions has made them serious competitors to traditional high-frequency transistors in many RF and microwave applications.¹ Of course, creating accurate models of these shrinking devices is an important part of modern computer-aided-engineering (CAE) design practices, and linearity is a key issue in these models especially for RF/microwave circuits, not only in high-power designs but in lower-power components such as low-noise amplifiers (LNAs).² There are a number of sources of distortion in a silicon CMOS transistor; among these are the transistor’s transconductance, g_m, nonlinear capacitances (mainly the gate-source capacitance, C_gs, and the gate-drain capacitance, C_gd), and the output conductance, g_ds. Because of nonlinear behavior, these parameters vary with the applied voltage on the gate and the drain of the transistor. While many previous studies aimed at analyzing CMOS transistor nonlinearity,^3-5 most of these studies looked at the distortion of the device as a whole using mathematical representations. As far as the authors are aware, no one has attempted physical level quantification of the sources of this distortion in the transistor model in the manner presented here.

Work undertaken in refs. 6 and 7 explained how table-based models can be built using symbolically defined devices (SDD) to represent each of the model’s nonlinear parameters individually and independently from one another. Quantifying contribution to distortion form MOSFET’s nonlinear elements was discussed as an application that demonstrates the need for such a model. This work builds on the work of ref. 6 by presenting the methods used to obtain linear representations of the nonlinear parameters in the transistor model. These linear representations of the model parameters are then used in the quantification process by switching the representation of the model’s parameters between their linear and nonlinear representations, as will be demonstrated. Voltage-controlled charge sources are used to represent nonlinear capacitances for this work.

Linearizing nonlinear elements of a transistor model implies that the resulting model’s characteristics are not a real representation of the modeled transistor but of an assumed transistor where the nonlinear parameters are made linear. The linearization mechanism should ensure that the fundamental response of the model should stay the same, and only its nonlinear behavior is affected. Discussion of the linearization process will be divided into linearizing the transconductance, linearizing the output conductance, and finally linearizing the nonlinear capacitances in the model

The transconductance, g_m, is essentially a voltage-controlled current source that describes the change in the small-signal drain current, i_DS, with respect to the small signal gateto- source voltage, V_GS . Therefore, when considering the linearization of the transconductance, two issues must be kept in mind. In order to correctly model g_m, linearly or nonlinearly, variance must be present. Therefore, replacing the SDD representing the transconductance current (I _gm) characteristics in ref. 6 with a current source at a single value (that of the respective operating bias point) or inserting the respective current value in the SDD as a single number are not valid methods of linearization, because no change is presented, and hence gm is not modeled correctly.

Also, it is well known that a voltage- controlled current source produces harmonics only if its current nonlinearly varies with its controlling voltage. If the current linearly varies with the controlling voltage, no harmonics are produced. The situation is different with nonlinear capacitances, as will be discussed.

In light of these two realities, and bearing in mind that the linearization should not affect the fundamental output of the transistor but only its nonlinear distortion, there are two options for linearizing the model’s transconductance: Either by using a voltage-controlled current source [such as the VCCS component in the library of the Advanced Design System (ADS) CAE software suite from Agilent Technologies] and setting its g_m to a value at the respective operating bias point, or by linearizing the values in the current characteristics data table.

The method of using a single-gm VCCS satisfies the variance condition in modeling the transconductance since g_m itself describes the change in I_DS with respect to V_GS. Also, since there is only one value of g_m at any input power, this change is linear. However, while a good S-parameter match can be obtained with this representation (since this value of g_m will be valid around close proximity of the bias point due to the very small signal used in the S-parameter test), the problem with this method is at high input power. When the input power significantly changes, the value of g_m set in the VCCS will no longer be valid and hence the fundamental output of the model is not expected to match that of the modeled transistor. This is because the total input voltage will expect to see another g_m value corresponding to the higher level input from the table that no longer exists. This problem is demonstrated in Fig. 1 where there is a good match between the fundamental output of the model and the transistor at low input power, but as the input power increases, the fundamental output of the model deviates further from the transistor’s fundamental output.

Linearization by changing the data in the Igm table works by changing the current level in each V_GS curve, of the transistor’s I_DS – V_DS characteristics of Fig. 3, when the transistor is in saturation. This method overcomes the drawback of the VCCS method in that several characteristic curves at different levels will be presented, from which gm is to be extracted, hence gm no longer has a single value. The strategy is to use the original nonlinear I_gm data table to plot I_gm versus V_GS as shown in Fig. 2(e), choose a V_GS bias point and plot a tangent of the I_gm versus V_GS characteristics at this point. The new values for the DC current in saturation are then taken from the linear tangent line rather than from the nonlinear tablegenerated characteristic line. A new linear-g_m table is then established. Implementation of this linearization method was designed with full automation, adaptability and reusability in mind. Figure 2 details the data display window coding equations that were used to perform this procedure and its results.

In Fig. 2(a), VDSpoint is a variable used to select a value from simulated drain voltages where the Igm - VGS characteristics used for linearization is to be plotted. Generally, any point in the saturation area of the highest V_GS characteristic curve is valid. VDSindex=find_index (indepVDS,VDSpoint) finds the sweep index of the selected V_DS value. indepVDS is used to remove the dependency of V_DS on V_GS that is generated from the sweep setup, but is undesirable in the manipulation of the functions. Parameter midVGS is a variable used to store the value of the chosen V_GS bias point at which the linear tangent line will be drawn. Here, it is done in the middle of simulated VGS values to get as maximally valid linearization as possible at a wider range of bias points, but any other VGS value can still be selected. midVGSindex= find_ index(VGS,midVGS) finds the sweep index number of this point.

The equations in Fig. 2(b) find the slope of I_gm - V_GS characteristic curve at the chosen V_GS bias point, needed for drawing the linear tangent. IgmChange=TableIgm [(midVGSindex+1),VDSindex]- TableIgm [midVGSindex,VDSindex] calculates the change in I_gm. The change is calculated between the selected bias point (specified by midVGSindex and VDSindex) and the next swept point on the VGS scale (specified by [(midVGSindex+1),VDSindex]), for extra accuracy. This setup ensures that this process is adaptable to any change in selected bias points. The change in V_GS is calculated similarly. The slope of the characteristic line is then evaluated in Slope=IgmChange/ VGSChange.

The equations in Fig. 2(c) plot the linear I_gm - V_GS characteristic line. The first four equations plot an initial linear line using the calculated slope, and make it overlap the characteristic line at the chosen bias point. LinearIgm= if (LinearLine<0) then 0 else LinearLine removes the negative part of the LinearLine and establishes 0 characteristics for Igm from the V_GS point at which the LinearLine crosses 0 I_gm, producing the linearized characteristic in Fig. 2(d).

The equations in Fig. 2(e) plot the linear I_gm - V_DS characteristic line. VDSSatPoint=VDS[SatPointIndex] finds the V_DS value at which saturation occurs. SatPointIndex specifies the knee of each V_GS curve at which the transistor enters saturation. VDSSat=VDSSatPoint[VGSindex] ensures that only one VGS curve (specified by VGSindex) is being handled every time. In LinearIgmVGS=if (VDS[VGSindex,::]<VDSSat) then Ids[VGSindex,::] else LinearIgm[VGSindex], the I_gm current level in each V_GS curve is modified to the new value taken from the linear tangent line after the saturation point (on the V_DS scale). This is done by searching all V_DS values if they were smaller or larger than the saturation point of that V_GS curve. If it is below, the value of LinearIgmVGS is taken from the original nonlinear current table (Ids[VGSindex,::]), if it is on or after saturation, the value of Igm is given its value from the linearized I_gm - V_GS characteristic line in Fig. 2(d). Fig. 2(f) demonstrates the change of Igm current level in saturation on a single VGS curve. With this value of V_GS, the transistor saturates at V_DS of 2.3 V. From this point forward, the current is replaced by its new value and the V_DS curve is modified. Figure 3 demonstrates how the I_gm - V_DS characteristics change using a number of V_GS curves. These new V_GS curves form the new linearized Igm data table that is used for quantification. Note that the actual work was performed on many more V_GS curves with 0.05-V steps in the range from 0 to 3 V.

Continue on Page 2