Frequency synthesizers are among the most challenging of high-frequency designs. Many approaches have been developed to generate clean output signals, although techniques that achieve low noise often suffer from limited tuning speed. Dr. Chenakin’s design team at Phase Matrix is developing solutions to these design trade offs, and Microwaves & RF spoke recently with him to hear his thoughts on the current state of microwave frequency synthesis.

MRF: With so many existing frequency synthesizer architectures, why is there a need for the new approach embodied in your latest products?

AC: The microwave industry feels persistent pressure to deliver higher-performance, higher-functionality, smaller-size, lower-power consumption, and lower-cost designs. However, the major technology challenge is to achieve fast tuning that is beyond the capabilities of YIG technology historically used in high-performance synthesizers.

MRF: What are the disadvantages of YIG technology?

AC: The main disadvantage is low tuning speed due to a high-inductance tuning coil required to generate a strong magnetic field. Besides this, YIG oscillators are traditionally known as expensive, bulky, and power-hungry devices. Although these parameters can be addressed in new YIG designs, the low speed is a fundamental problem inherent in YIG technology.

MRF: What switching speed requirements are you seeing at present?

AC: The time spent by the synthesizer jumping between frequencies becomes increasingly valuable since it cannot be used for data processing. A simple example: let’s assume you are making a 401 point sweep measurement on an RF IC test using a source with 25 ms switching speed (that is a typical number for a YIG-based synthesizer). In this case, your dead-time per measurement exceeds 10 sec—just for one measurement! If you can use a synthesizer with 100 us switching, your dead-time is reduced to 40 ms. It is quite a significant throughput improvement if you run continuous measurements. Thus, while many systems still work adequately with millisecond switching speeds, newer requirements demand microsecond operation together with comparable spectral purity (such as phase noise and spurious) of the low speed designs. Target numbers are currently in the range of tens of microseconds.

MRF: What technologies can be used to achieve such speed?

AC: Direct analog, direct digital, and indirect (or phase locked) approaches are used for modern synthesizers. Each has trade offs. For example, direct-analog synthesizers can provide the best performance in terms of speed, but they are complex and expensive. Direct-digital synthesis (DDS) is fast and reasonably priced, although it still needs to improve in terms of frequency coverage and spurious performance. Thus, the most exciting near-term solutions are likely to be associated with VCO-based PLL synthesizers.

MRF: What are the advantages of the VCO-based designs?

AC: Unlike YIGs, VCOs are capable of switching speeds in the microsecond range. With VCOs available as ICs, size, power consumption, and cost are negligible in comparison with YIGs. Besides, VCOs are much less sensitive to microphonic effects due to their extremely low weight and profile.

MRF: VCOs tune faster than YIGs; however, their phase noise is significantly worse. How do you achieve “YIG-like” noise levels without a YIG?

AC: The “YIG-like” noise performance varies from definition for a certain offset and output frequency with, let’s say, 5 GHz. Although, the numbers differ from vendor to vendor, but typical numbers might be -105 and -125 dBc/ Hz, respectively, offset 10 and 100 kHz from a 5-GHz carrier. Current VCOs cannot provide this level of performance, although you can achieve these noise levels by other means, such as by relying on your reference to suppress the VCO noise. Assume your synthesizer includes a 100-MHz oven-stabilized crystal oscillator (OCXO) with -160 dBc/Hz noise floor. Using a standard 20-dB/decade phase-noise degradation rule, you can potentially get -126 dBc/Hz at 5 GHz at both 10 and 100 kHz offsets that corresponds or even exceeds the performance of traditional YIG-based designs.

MRF: But is it worse at 1 MHz offset?

AC: It is worse with the same low-cost reference. However, it will be significantly improved with a higher-cost -176 dBc/Hz reference. A better way is to use a combined reference such as an OCXO and CRO (or SAW) oscillator combination. For example, a 3.2 GHz CRO locked to the same OCXO exhibits better than -150 dBc/Hz phase noise at 1 MHz offset.

MRF: Should the PLL filter bandwidth be wide to utilize the low noise reference benefits at these offsets?

AC: The loop filter bandwidth must be wide enough, a few MHz or more, to wash out the VCO noise and reach its thermal noise floor. Besides, we are assuming that the reference signal translation is not affected by the synthesizer system (or PLL) noise floor. Nevertheless, the net effect is evident: VCO-based designs can potentially achieve faster tuning speeds and comparable phase noise characteristics of YIGs without the size and power consumption of YIGs.

MRF: Tell us about your technology for low-noise signal translation.

AC: We have developed a novel, patentpending, phase-refining technique to reduce the synthesizer PLL residual noise floor. As you know, the phase noise of a conventional single-loop PLL is proportional to the division ratio of the divider inserted into the loop. In general, by minimizing the ratio, you can improve phase noise. Our technology takes a more radical step by completely removing the divider from the PLL feedback path. Moreover, it inverts the PLL division ratio by applying multiplication within the PLL that improves both phase-noise and spurious characteristics at the same 20 dB/decade rate.

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