Phase locked loops (PLLs) are common to many communications systems, including in WiMAX Access Points (AP). By performing an analysis of the phase-noise contributions of the PLLs within a WiMAX AP frequency chain, which is essentially the string of PLLs in the system starting with the frequency reference in the controller and ending with the transmitter local oscillator (LO) in the RF head, it is possible to better understand the impact that each PLL has on overall system performance.

Figure 1 provides a block diagram for a hypothetical frequency chain in a WiMAX AP. Each box in the block diagram represents a PLL that serves a unique purpose in the AP design. Since all the PLLs are connected in series, the signal and noise at the output of each PLL feeds the input port of the next PLL in the chain. All seven PLLs in this example contribute to the ultimate signal and noise performance at the output of the chain. For practical analysis purposes, the chain begins with the reference oscillator in the site controller. This special loop is locked to the Global Positioning System (GPS) receiver, but the loop bandwidth is so low that the only noise at the site controller reference PLL’s output is the phase noise of the oven-controlled crystal oscillator (OCXO).

To review the essentials of PLL design,^1-3 a PLL is a control loop that typically locks the phase and frequency of a tunable signal source, such as a voltage-controlled oscillator (VCO), at the output of the loop to the frequency and phase of a presumably stable signal at the input of the loop. Figure 2 shows the major elements of a PLL. The frequency of the loop output (FOUT) is related to the frequency at the loop input (FIN) by

where
N = the loop frequency multiplication factor,
R = the reference oscillator divider, and
P = the output divider, which is optional.

Designing for a higher-than-needed frequency and then dividing the output to reach the desired frequency is an approach that can be used to improve noise performance. Post-loop frequency division can also be used to lower the output frequency that is sometimes needed by the reference divider of a subsequent stage. Most, if not all, PLLs act as phase-noise filters to the input signal (with each PLL exhibiting a unique lowpass response) and also as phase-noise generators. Some important points to note about PLL noise theory are that:

1. Each PLL has a unique lowpass response, most often characterized by the closed-loop 3-dB banwidth.
2. At frequencies above the loop bandwidth, the loop attenuates the phase noise of the input signal and also attenuates the phase noise of the phase detector and charge pump inside the loop.
3. At frequencies below the loop bandwidth, the loop attenuates the phase noise of the VCO or other voltage-controlled element in the loop.

The choice of loop bandwidth is often based upon achieving optimal noise at the loop output. Most often this is the point where the curve of the multiplied reference noise and the PLL noise floor crosses the curve for the free-running VCO’s noise on a phase-noise-versus-frequency plot. At other times, this noise-optimal bandwidth must be compromised in order to meet loop lock-time requirements. Charge pump settings, choice of dividers, and loop filter components are chosen to design a particular loop bandwidth while meeting noise, lock-time, and stability requirements. This design process is well understood, and many software programs are available from PLL IC suppliers to aid in PLL design.^4,5

Design parameters chosen for each PLL can be entered into commercial computer-aided-engineering (CAE) software, such as the Advanced Design System (ADS) software from Agilent Technologies, to verify loop response (bandwidth and stability).⁶ This should be done for each PLL in the frequency chain. Figure 3 shows an example simulation model for a 50 MHz RF head reference PLL, while Fig. 4 shows example simulation output results.

Simulation results show that this loop has reasonable stability, evidenced by the low gain peaking shown by marker 1 on the red curve in in Fig. 4 (less than 2 dB) and the phase margin result of 48.2 deg. Phase margin of 45 deg. or higher is considered stable for most designs. Furthermore, the simulation result shows that the loop’s 3-dB closed-loop bandwidth is around 26 Hz. This was purposely designed to be quite low in order to filter out nearly all of the incoming phase noise on the reference source. To validate simulations, measured data for closed-loop responses should be compared with the simulation results for each PLL in the chain. Accurate simulations of loop response and stability are essential for achieving accurate cascaded loop response simulations (which include the phase noise of all PLLs in the chain).

Armed with the design parameters for each PLL, a commercial CAE program can also be used to verify output phase noise. This should also be done for each PLL in the frequency chain. An example simulation model is shown in Figs. 5 and 6 along with example simulation output results in Fig. 7.

The simulation file shown in Figs 5 references a simulation schematic (called Ref_Synth_50 MHz in Fig. 5, and fully expanded in Fig. 6). This is controlled by the AC controller AC1 in Fig. 5. Designing simulations in this modular fashion allows PLL modules to be designed that can be used in other simulations. These simulations are behavioral in nature rather than at the circuit level, but they are valuable for predicting PLL behavior. As with all simulations, the validity of the output depends on the accuracy of the inputs.

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