Widespread adoption of wireless technology has created market demands for highly integrated circuits, such as a transmitter, receiver, and frequency synthesizer on a single chip. Silicon CMOS technology has made such integration possible with the exception of the power amplifier (PA), which is still typically implemented in non-CMOS technologies. Ideally, silicon CMOS PAs can be developed for tight integration with other wireless building blocks. Some design strategies for creating CMOS PAs follow.

Power amplifiers involve a balancing of many different parameters, including power-added efficiency (PAE), linearity, maximum output power, maximum stable gain, input/output matching, stability, heat dissipation, and breakdown voltage. As with many RF component designs, these requirements are often in conflict with one another. For example, achieving good linearity usually comes at a cost in PAE. Linearity is typically evaluated in terms of output third-order intercept (OIP3), 1- dB compression point (P1dB), adjacent- channel power ratio (ACPR), AM-to-AM distortion (AM/AM), and AM-to-PM distortion (AM/PM). Improved linearity is usually achieved by backing off an amplifier’s output power from its saturated output level, and more DC power will be consumed in order to meet a given linearity requirement.

Although many such trade-offs face a PA designer, amplifier circuits have been well researched over the years with many different design approaches documented. ^3,4 There are many interesting topologies at a designer’s disposal. In order to explore the possibilities of PAs fabricated with silicon CMOS, singleended CMOS PAs will be examined first, followed by differential CMOS PAs. This report will cover two simple topologies that provide improved linearity, and will conclude with a discussion on high-efficiency Class E and Class F CMOS PAs.

Single-ended Class AB PAs have been reliable performers in a wide range of applications for some time.^5-7 The arrangement is actually a hybrid combination of Class A and Class B approaches. In a Class A PA, the power transistor is on 100 percent of the time with bias current never turned off. A Class A PA typically delivers close to maximum power with outstanding linearity, although the best theoretical efficiency for this approach is only 50 percent.

A Class B PA achieves improved efficiency by biasing the power transistor at its turn-on threshold. The output of the driver amplifier will turn on and off the final power-amplifier stage, with the final-stage power transistor on only 50 percent of the time. Because of this, the efficiency of a Class B design can be improved to 78.5 percent.

A Class AB amplifier reaches a compromise between the Class A and Class B approaches. The transistor is biased slightly higher than its turn on voltage, but not quite to turn it on all the time. A Class AB PA is typically implemented in multiple stages (Fig. 1) for improved PAE, not just efficiency. In this design, device M1 is the driver FET while device M2 is the output-stage FET. The input, output, and inter-stage impedance matching can be done with an L, T, or pi network. Drain-to-gate feedback is often used in Class AB designs for improved stability; such feedback also simplifies impedance matching. In this particular design, resistors R3 and R5 and capacitors C2 and C6 are the feedback elements. Resistors R1 and R2 and resistors R4 and R5 are simple resistor divider networks used to bias the transistor. By using different resistor dividing ratios, the basic circuit of Fig. 1 can be converted to many other PA configurations, including Class A, Class B, and Class C designs.

CMOS transceivers are typically implemented as differential circuits to reduce susceptibility to commonmode noise. Fig. 2 shows a common differential PA.^10-12 It is essentially two singleended PA in parallel. The resistor dividers are implemented with FETs M5 and M6 as well as M7 and M8. In order to connect the amplifier with an external filter, a balanced (differential) input filter is needed. The filter’s output can be unbalanced to interface with a single-ended antenna, or designed as a balanced output for use with a dipole-type antenna.

Since single-ended filters and antenna are widely used, a practical design would integrate a balancedunbalanced (balun) transformer inside the PA. Fig. 3 shows a generic differential PA with an integrated balun. The design has been modified from the gain block topology of Fig. 2 and employs a cascode topology. The cascode approach reduces the gate-drain capacitance (C_gd) Miller multiplication effects and provides added isolation between the input and output ports, improving amplifier stability without using feedback.

This design approach also improves the gain compared to the single transistor stage. Since the similar circuit topology is used in this circuit, only one stage is discussed more in details. The lower cascode transistor M1 is biased with current mirror configuration. M1’s bias current is a scaled version of the bias current I2 via transistor M10. The added benefit of this "diode" type bias is that the bias circuit tracks the bias condition of the power FET, preventing the occurrence of any "thermal runaway" problems. Like device M3, the top cascode transistor is biased in the saturation region by simply tying its gate to the power supply. The gate voltage V_gd is thus always below the threshold voltage, V_t , meeting the saturation region requirement. The output balun, X1, can be implemented by means of a spiral integrated inductor. Capacitors C5 and C6 are matching elements for the balun input. There are many theories and techniques on the design of an integrated balun, which is outside the scope of this paper. Low-loss integrated baluns have been reported in many designs that are suitable as examples.^8,9

Simple techniques can be used to improve CMOS PA linearity without consuming additional DC power. Fig 4a and Fig. 4b shows two such topologies. The first uses a "diode" type linearizer (Fig. 4a). As the PA output is increased, the transistor’s gain begins to drop (AM/AM distortion) and its phase begins to increase (AM/PM distortion). Fortunately, the FET-based diode responds with the opposite behavior under those conditions. It expands the gain while reducing the phase. By means of careful device characterization and design, the linearity of the PA can be improved.^14,15 The circuit in Fig. 4a is a slight modification of the class AB PA presented earlier. Transistor M3 serves as the linearization "diode."

Another simple approach for improving PA linearity explores AM/PM compensation. Most AM/PM PA distortion comes from the variable gate-to-source capacitance (C_gs). By cancelling the variable Cgs from the NMOS FET with a PMOS FET, the linearity of a CMOS PA can be improved.16 A generic design is shown in Fig. 4b with transistor M3 serving as the compensation capacitor. Both linearized circuits of Figs. 4a and 4b can be implemented with minor modifications in the output power stage of the basic CMOS PA format.

Class AB, B, and C PA topologies improve the efficiency by reducing the conduction angle of the FET. In addition, Class E and F topologies can also offer improved efficiency. In theory, Class E and F topologies can approach 100-percent efficiency. In a Class E PA, the power transistor is switched on and off, with the intention of reducing the overlap between the current and voltage waveforms crossing the FET’s drain and source. The overlapping region represents the power not delivered to the load, so as little overlap as possible is desirable. By switching the power transistor on and off, either the current or the voltage are on one at the time, but not both at the same time.

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