Transponder design for radio-frequency-identification (RFID) circuits must overcome many of the challenges faced by other low-power electronic applications. RFID transponder circuitry must be low in cost, and must operate over long periods of time on limited power sources. Earlier in the article series (Microwaves & RF, September 2006, p. 57 and October 2006, p. 82), basic design strategies were presented for designing RFID transponder integrated circuits (ICs) and how they could be applied in different circuits. In this final installment of this article series, some advanced RFID transponder design strategies will be explored, with chief goals of saving power and saving money.

The cost of a transponder design depends on several factors and not just the cost of the silicon alone. In fact, the costs of the chip-fabrication process (in terms of its complexity and maturity and the resulting yield) can generally be controlled by the circuit designer. As a rule of thumb, the economies of RFID for a supply-chain application begin to fall short when the die area exceeds 1 square millimeter.

An RFID transponder's power-supply requirements can present a difficult-to-predict challenge for a designer since an RFID tag's power varies over roughly three decades when moving from the minimum to the maximum range of the system. Although the typical power available for UHF RFID tags is on order of a hundred microwatts, the problem is not limited to power dropouts alone. Even at short distances, it is possible to put sufficient power into the tag to induce electrical overstress. Tags also have to work over a nominal temperature range from –25 to +40°C and an extended temperature range from –40 to +65°C based on the EPC Gen2 standard.

The cost and power requirements greatly impact the choice of technology used to fabricate an RFID transponder IC. As noted in the earlier parts of this article series, Schottky contacts provide low turn-on voltage, low junction capacitance, and high current drivability in RFID transponder designs. Alternatively, there have been efforts to employ newer technologies such as BiCMOS and silicon-on-sapphire (SOS), which offer excellent low power performance. But there are downsides to each approach. Schottky contacts are not routine in CMOS processes, and usually require post-processing steps. The other technologies, BiCMOS and SOS, are too expensive for most RFID transponder applications.

Another option for implementing low-power circuit requirements is dynamic-threshold-voltage MOSFET (DTMOS) technology. It can be fabricated inexpensively using bulk silicon CMOS technology. Both advantages are well suited for the development of the next-generation UHF RFID transponder, which is described in this article. This article will first introduce the fundamentals of DTMOS. Then, the DTMOS implementations in the digital, analog and RF domains will be highlighted as UHF RFID transponder contains circuitries covering all three domains. Finally, the chip implementation of DTMOS-Band-Gap reference circuit of UHF RFID transponder, following EPC Gen2 specifications will be demonstrated.

DTMOS is basically a MOS transistor with an interconnected well and gate (Fig. 1). For twin-well p-substrate CMOS processes, only P-type DTMOS can be used due to the fact that only their N-wells can be controlled and fabricated independently, since the P-well of N-type DTMOS has a common and low-ohmic path to the P-substrate. However, N-type DTMOS is available in processes with deep N-well feature. DTMOS operates like weak-inversion MOS operation, with similarities to bipolar operation in a lateral PNP. The drain current of a weak-inverted MOS transistor and the collector current of a lateral PNP (both in saturation) are given by:

where:
F = F_BJT = V_BE
for a bipolar transistor and
F = F_WIM = [(V_GS– V_T).C_OX/(C_OX + C_depletion)]
for a weak-inversion MOS transistor.
The value of the depletion capacitance depends on the width of the depletion layer, which in turn depends on the well doping characteristics and the voltage drop in the silicon near the source junction. Hence, the factor depends on the applied well-source voltage and on the applied well-source voltage via the threshold modulation effect.

DTMOS can be viewed as a lateral bipolar PNP with an extra gate over the base. Based on this view, DTMOS’s drain current is primarily determined by the voltage across the source-well junction, which results in an ideal exponential (bipolar-like) relation between V_GS and I_D. Due to the presence of the interconnected gate-well, there is a built-in voltage F_GW between the gate and well. Voltage F_GW is subdivided over the gate oxide and over the silicon due to capacitive division. Denoting the voltage drop in the silicon due to F_GW as the barrier lowering voltage F_b1, it can be shown that the drain current of a DTMOS is:

The barrier lowering voltage Fb1 is given by:

which is a function of FGW and of a number of process parameters. Derivations from refs. 1-4 show that:

The key results from these derivations are as follows:
• The apparent bandgap of a DTMOS device is 0.6 V compared to 1.2 V for a silicon PN junction.
• The DTMOS device follows an ideal exponential characteristic [I_D a exp(qV_GS/kT)]
• The DTMOS device’s lateral current is a factor of exp(qFb1/kT), which is larger than ordinary lateral PNP counterpart.
• The apparent bandgap voltage is temperature dependent.