Frequency synthesizers are fundamental building blocks in wireless systems. Market pressures drive higher levels of integration in support of multiple wireless standards. But each wireless standard requires a specific crystal reference frequency and specific channel spacing. Integer-N frequency synthesizers can achieve the small step sizes required in support of multiple standards, but with high phase noise. Fortunately, a sigma-delta fractional-N frequency synthesizer can combine the small step size with low phase noise inside the loop bandwidth, although with the cost of introducing out-of-band quantization noise. The development of a second-generation sigmadelta fractional-N frequency synthesizer, however, provides the flexibility and performance needed in a single design for multiple wireless-communications standards (refs. 1-5).

Although the sigma-delta fractional-N frequency synthesizer approach is a significant improvement over integer-N synthesizers, a sigma-delta modulator generates quantization noise outside the loop bandwidth. This unwanted noise can be filtered out by narrowing the loop bandwidth or by adding additional parasitic poles to quickly roll-off the quantization noise. Unfortunately, this requires more pins and off-chip components. More parasitic poles cause uncertainty in loop-dynamics and stability making direct modulation impractical when the desired data rates are near or above the loop bandwidth.

Frequency-switching time is also an issue in any synthesizer design for wireless standards. A synthesizer requires a narrow loop bandwidth to attenuate the out-of-band quantization noise whereas fast switching times require the synthesizer with a wide loop bandwidth. To achieve the desired switching speed and phase noise for a given standard, it is possible to use multi-state loop filters to acquire lock quickly. One state would be wideband for acquisition and the other would be narrow for phase noise. When a multi-state loop filter changes state, incorrectly charged capacitors (parasitic or intentional) can be present unless the multi-state loop filter is carefully designed. These capacitors can move the synthesizer away from the desired lock point just as it switches to a low bandwidth, making acquisition time specifications harder to meet.

Large resistors in analog loop filters add out-of-band noise to the synthesizer. Small resistor values require large capacitors to obtain the same time constants, forcing the use of off-chip capacitors. The on-resistance of switches in multi-state loop filters must be small, implying large switches. This causes more capacitive feedthrough when the filter changes state. A two-state loop filter can be challenging for even one mode of a single wireless standard, let alone for multimode use. Different standards call for different loop bandwidths and VCOs, making the challenge to bring everything on a single chip difficult.

A 2-GHz synthesizer with a 26-MHz reference frequency and a loop bandwidth of approximately 45 kHz would require the loop filter component values listed in Table 1. The loop filter components were calculated for the passive loop filter shown in Fig. 1. While resistor R1 could easily be integrated, the main capacitor C1 would require an impractical size of approximately 15 X 10⁶ µm² (3900 X 3900 µm) in a typical 0.35µm BiCMOS process.

The practical requirement for having to leave loop filters off-chip results in several design issues. External components are expensive and occupy printed-circuitboard (PCB) space. The pads used to interface with off-chip components are in high demand as many chips are pad limited. Costs can be increased if additional pads force the use of a larger package. Also, the edge of the chip is prime real estate. External loop filters force the synthesizer to be in competition for edge space, subsequently making the layout more difficult.

Among the most challenging elements of synthesizer design is the loop filter. To alleviate loop-filter constraints, it is desirable to integrate the loop filter on the same chip as the synthesizer, and to make it programmable. An improved synthesizer architecture developed by Kaben Research (www.kabenresearch.com) called the "second-generation sigma-delta synthesizer" (Fig. 2) implements these two measures. It differs from precursors by integrating a sigma-delta phase detector and digital loop filter. A digital representation of the VCO phase and frequency is obtained using the sigma-delta phase detector and digital logic.

Since the phase- and frequency-measurement results are in the digital domain, it is possible to integrate a programmable digital loop filter and a digital frequency acquisition loop. This reduces the analog component of the loop filter to a single small-valued capacitor that can easily be integrated on chip. This capacitor is placed at the output of the current-mode DAC.

Apart from providing a digital representation of the VCO phase, the sigmadelta phase detector also features fractional phase resolution. This reduces the density of the phase quantization noise at the output of the synthesizer. In a sigma-delta fractional-N synthesizer, a sigma-delta modulator controls an integer-N divider in order to obtain fractional frequency resolution. The resulting quantization phase noise at the output of the synthesizer is given by:

where:

Δ = the quantization step size of the sigma-delta modulator,

OΔΣ= the order of the sigma-delta modulator, and

F_REF = the reference frequency.

In this case, Δ has a step size of 1 VCO cycle, which is equal to 2 π radians. The sigma-delta phase detector introduces a phase quantization noise equal to: