Radio-frequency identification (RFID) transponder design techniques were introduced last month, in the opening installment of this two-part article series. This month more advanced methods will be explored for enhancing the performance of UHF RFID transponders, using four design examples in Germany, the United States, Italy, and Switzerland.

The German group was involved in pioneering work in UHF RFID, developing a variety of efficient circuit design techniques. However, their work required the use of a nonstandard 0.5-µm CMOS process. The US group proposed a low-cost design using Schottky diodes, employing novel data readout circuit and the capability of boosting the data rate to 10 Mb/s. The Italian group focused on low-power consumption and achieved submicrowatt power consumption with their digital module, based on AMI's 0.5-µm CMOS process. The Swiss group developed their UHF RFID transponder using silicon-on-sapphire (SOS) technology and achieved the farthest detection range.

Pioneering work was performed at Atmel (Heilbronn, Germany) in 2003.¹ The RFID transponder chip was implemented with AMI's 0.5-µm dual-poly dual-metal silicon CMOS technology. The chip outperformed other reported RFID integrated circuits (ICs) by a factor of 3 in terms of required receive power level for a given base-station transmit power and tag antenna gain.

The German design group used a special CMOS fabrication process that contained Schottky contacts. The Schottky diodes are used in the rectifier structure, which is a five-stage Dickson charge pump. The resulting design delivered high saturation current (I_s), low junction capacitance (C_j), and low parasitic capacitance (C_sub). Since the input module consists of Schottky diodes, the chip features input impedance with quality factor (Q) as high as 30. The high Q increases the incident voltage level, a desirable trait for these UHF RFID transponders. The high Q is also supported by careful layout with low series resistance and low capacitances for on-chip interconnections and high-Q poly-poly capacitors. Their work also demonstrated that circuit performance could be improved by using a large aspect ratio and multifinger layout approach to minimize Rs. Their work did not mention the need for a voltage regulator.

Phase-shift-keying (PSK) modulation is employed in the reverse link (the modulator). Modulation is achieved by using an MOS varactor to change the input impedance between two states. The modulating reactance is achieved with the help of accumulation mode MOS varactor M1 and two poly-poly capacitors, C1 and C2 (Fig. 1). The capacitance of the MOS varactor is shifted from its maximum and minimum values by applying maximum and minimum voltage values to the varactor.

For control over the backscatter bandwidth, two driving inverters M4-M5 and M6-M7 are biased in the triode region, using biasing transistor M2 and M3 to control the current flow. The remaining four transistors, M8, M9, M10, and M11, form a buffer to drive logic signals coming from the digital block. The use of PSK leads to simultaneous higher power efficiency for DC power and high-modulated backscatter power.

The demodulator module is comprised of an envelope detector and pulse width demodulator (Fig. 2). The envelope detector uses the same structure as the rectifier, using a two-stage Dickson charge pump and smaller poly-poly capacitors. These capacitors together with the current sink determine the minimum gap width that can be detected by the circuit. The gaps between pulses are selected to be approximately 4 µs long, which is long enough to comply with stringent bandwidth regulation in Europe, but short enough to maintain continuity in a transponder power supply. The current sink serves as a large dynamic resistance, acting as a lowpass filter that limit the bandwidth and width of gaps detectable. The filtered RF envelope signal is then fed to a hysteresis comparator, which incorporates a Schmitt trigger to transform the RF envelope into digital high-low pulses. Incoming pulses are used for the system clock in the digital module and internal clock generation center, where each rising edge denotes the arrival of new bit. The integrator is then used to measure the length of the pulse, which is measured by a simple discriminator circuit to determine 1 and 0 data. Careful planning of protocol and control logic resulted in a power consumption of roughly 2.25 µW during normal operation, and 3.75 µW during write operation with a 1.5-V power supply.

Researchers at the University of Maryland developed a somewhat simpler design based on a rectifier and demodulator using Schottky diodes, similar to the work done by the German group. The Schottky contacts were fabricated " inhouse" using post-fabrication techniques employing focus ion beam (FIB) methods. The design also featured novel data readout circuitry that can boost data rates to 10 Mb/s. The transponder architecture is simple, designed for a read-only tag with no digital protocol and electronically erasable programmable readonly memory (EEPROM). ² The RFID system is designed for half-duplex operation. The interrogating protocol uses Texas Instruments 134-kHz system protocols. The reader emits a continuous-wave (CW) signal to power up the tag. Once powered up, the transponder will transmit back its identification (ID) content via backscatterer. Since reader commands are not supported, a demodulator circuit is not needed.

A Dickson charge pump is used to construct the rectifier, with a stacked-diode architecture for the voltage regulator circuit. Seven Schottky diodes are stacked together to limit the DC output below 1.5 V. The regulator will not turn on if the generated voltage is lower than 1.5 V. The Schottky diodes are fabricated using a post-fabrication process with FIB. The design group has experienced successful Schottky fabrication with three different silicon CMOS processes, 1.5, 0.5, and 0.3 µm processes. ³