Direct digital synthesizers (DDS) are commonly used for sinusoidal signal generation in RF communication systems and test equipment. An integral component of DDS is the digital-to-analog converter (DAC). Although a DAC is intended to perfectly reproduce an analog signal from its digital equivalent, the conversion process is rarely perfect. The DAC's digital resolution (number of bits) is a limiting factor that introduces quantization errors resulting in a noise floor. Other errors, such as linearity errors, create undesired harmonics in the DAC/DDS output spectrum, limiting the spurious-free dynamic range (SFDR). Fortunately, a DDS architecture has been developed that reduces harmonic spurious signals due to the non-ideal characteristics of the DAC, resulting in a significant improvement in SFDR performance.

In general, harmonics can usually be filtered without much difficulty. However, the conversion of a digital signal to an analog signal by a DAC lies in the realm of sampling theory. This means that harmonic signals do not always appear at obvious frequencies according to the rules of digital signal processing (DSP). For example, suppose a DAC sampling at 100 MHz generates a sinusoid with a frequency of 26 MHz. The third harmonic would be expected to appear at 78 MHz where it can be easily filtered. In fact, a third-harmonic image will also appear at 22 MHz because of the effects of sampling. Because it is only 4 MHz away from the fundamental signal, it is difficult to filter without also attenuating the fundamental signal. Obviously, if harmonics could be selectively attenuated, the SFDR performance of the DAC could be improved.

As mentioned earlier, harmonic distortion introduced by the DAC is usually the limiting factor of SFDR performance in a DDS. Present solutions for improving SFDR involve frequency planning and/or the addition of external filtering at the DAC outputs.

An alternative solution is to predistort the digital signal as it arrives at the input to the DAC in such a way that it eliminates the harmonic signal, a technique that is a variation on a method called destructive interference. Summing two sinusoids of the same frequency, but with equal and opposite amplitude, will result in cancellation of both sinusoids.

The mathematical explanation of this concept is best understood by first considering the signals concerned in the context of a DAC-generated sinusoid. The first is the primary sinusoid with amplitude P and frequency wP. An arbitrary spurious signal has amplitude S and frequencyw_S. The frequencies of the primary and spurious sinusoids are related by w_S=Nw_P (where N>1). Furthermore, in the special case where the spurious sinusoid is harmonic, N is an integer greater than 1. The amplitudes of the primary and spurious sinusoids are related by S = aP, where typically a <<1. Next, a canceling sinusoid of amplitude C with the same frequency (w_S) as the spurious sinusoid is introduced, but offset from the spurious sinusoid by some arbitrary angle q. The amplitudes of the canceling and spurious sinusoids are related by C = bS. However, since the spurious sinusoid and the canceling sinusoid both possess the same frequency, they combine to form a single resultant sinusoid of amplitude R and frequency w_S Combining the relationships between the amplitudes of P, S, and C along with the fact that the spurious and cancelling signals are offset by the angle q, it can be shown that the amplitude of the resultant sinusoid (R) is given by:

The most notable feature of this expression occurs when the amplitude of the canceling sinusoid is identical to the amplitude of the spurious sinusoid and phase shifted by 180 deg. This occurs when b = 1 and q = 180 deg. (p rad). Under such conditions, R = 0.

With the above expression for R, it is instructive to examine the quantitative relationship between R, b and q. This is best done by considering the ratio, R/aP, which gives the amplitude of the resultant sinusoid relative to the amplitude of the spurious sinusoid. This ratio, expressed in decibels, is:

Figure 1 demonstrates the way in which R varies as a function of both b and q. The axis labeled "Amplitude Error" equates to b values that deviate from unity over a range of ±5 percent. The axis labeled "Phase Error" equates to q values that deviate from 180 deg. over a range of ±5 deg. Notice that the four corners of the surface plot are local maxima and register approximately -20 dB. This means that if the phase of the canceling signal is within 5 deg. of being completely out of phase with the spurious signal and is matched to within 5 percent of the amplitude of the spurious signal, then the resultant signal can be expected to achieve a 20 dB amplitude reduction with respect to the level of the original spurious signal.

A basic DDS architecture is comprised of an accumulator, phase-toamplitude converter, and a DAC. This structure is ideally suited for the implementation of the destructive interference concept. A cancellation signal can be generated by adding a duplicate DDS path, excluding the DAC (Fig. 2). However, two modifications must be made to the primary DDS path. The first is the inclusion of an adder inserted between the primary phase-to-amplitude converter and the DAC in order to facilitate the combining of the cancellation signal with the primary signal. The second is a multiplier that has the primary frequency tuning word as one input and a user-specified frequency scaling value as the other input. This provides the ability to adjust the frequency of the cancellation signal. However, because the frequency of the cancellation signal is always an integer multiple of the primary signal (i.e., a harmonic), the design of the multiplier is somewhat simplified (integer rather than floating point).

In addition to the two changes in the primary DDS path, the "cancellation" DDS also requires two modifications (Fig. 2). The first is the insertion of an adder between the accumulator and the input to the phase-to-amplitude converter. This allows the user to apply a phase offset ( ) to the cancellation signal relative to the primary signal. The second is a multiplier between the output of the cancellation phase-to-amplitude converter and the input to the adder that now precedes the DAC. This allows the user to scale the amplitude of the cancellation signal.