Software-verification tools support the constant evolution and improvement of many integrated circuits (ICs). For example, these tools have enabled designers to shrink the size and cost of personal-handy-phone-system (PHS) ICs while increasing the level of integration. Typically, PHS transceivers are implemented as a multi-RF chip solution. To satisfy the growing demand for lower-cost PHS handsets in China and other countries, however, engineers from Microlinear and Cadence have applied software-verification tools to develop a single-chip PHS transceiver.

The block diagram of the singlechip transceiver is shown in Fig. 1. Clearly, design tools were needed to minimize the complexity that is derived from having a large number of components and digital gates. The transceiver incorporates a low-IF receiver architecture demonstrating ?105 dBm sensitivity, a transmitter with an on-chip ³+21-dBm output PA, and a single fractional-N synthesizer achieving <30-µs lock time for fast handoff capability. The architecture's high level of integration and complexity resulted in a 2X to 3X increase in digital-logic content—from approximately 3 kgates to nearly 13 kgates. It also resulted in significantly larger die size. The design therefore required the adoption of new analysis tools as well as automated methodologies for synthesizing, placing, and routing the digital logic.

The individual parts of this transceiver-IC also are very complex. The receiver subsystem, for example, consists of an RF I/Q downconverter. The RFdownconverter section, in turn, consists of a differential low-noise amplifier (LNA) and an image-reject mixer. The required sensitivity is ?100 dBm and blockers can be as high as 50 dBm. As a result, the RF front end requires a minimum instantaneous linear dynamic range in excess of 53 dB. The IF upconverter subsystem consists of a 450-kHz bandpass filter (BPF), IF amplifier, upconverter, 1.2-MHz BPF, second IF buffer, and polyphase network.

Transmitter Design
The transmit-circuit block diagram is also shown in Fig. 1. The transmitter is designed to accept DC-coupled, quadrature PHS baseband inputs. The baseband signals are buffered and applied to the quadrature modulator. There, they are combined and directly converted to the 1.9-GHz RF. With the help of design tools, both the PA and I/Q modulator eliminate the traditional filter that is seen between the modulators and PA in PHS and many other transmit designs.

To achieve high linearity, the modulator was designed with a topology that is similar to the one used in the RX. The TX chain includes a digitally controlled, 32-dB programmable-gain amplifier (PGA). This PGA is used to shape ramp profiles during transmission power-up and power-down cycles. It also functions as a digital control for setting the output power. The integrated PA consists of two stages of Class A/B amplifier with external inductors for matching and DC supply.

PLL Design
To meet the challenging phase-noise and switching-time requirements of the PHS standard, a highly configurable fractional-N architecture was selected. Fractional-N synthesizers break the traditional tight relationship between PLL bandwidth, resolution, and reference spur level. A fractional-N synthesizer provides the opportunity to have extremely fine resolution while simultaneously keeping a large loop bandwidth. Compared to their Integer-N counterparts, fractional-N synthesizers have a smaller settling time and lower closein phase noise. Yet these features come at the expense of higher out-of-band noise and spurs.

The digital-control-logic block controls the many programmable blocks within the design. Registers are provided on the chip to allow the control of many of the parameters within the PLL, receive, and transmit blocks. For example, the gain of the receive path can be controlled at several stages by setting the gain of the LNA or one of several VGA stages. The control logic does all of the required power management for the IC.

Methodology Overview
In the design of mixed-signal ICs, analog functions dominate the die area. As a result, analog IC designers often design the digital portions as well. A common practice is to create a small standard-cell library (e.g., about 40 cells) and place logic symbols on a schematic.-The designer will then do a Verilog gate-level or transistor-level simulation. Because of the small gate counts (<10 kgates), the layout is done by hand instead of using industry-standard digital-block place-and-route tools.

This type of manual logic design and layout process can still be very time consuming, however. For a 5.8-GHz digital-cordless-telephone chip that used this methodology, the design and layout of the logic blocks for the PLL synthesizer and control logic took over four man-months of effort. All of the logic, including a scan chain for ATE, was designed manually. All together, these blocks involved about 3000 two-input, NAND-gate logic equivalents.

Once the gate counts begin to exceed 10 kgates, as they did on the current design, manual design and layout techniques become impractical. Another challenge is that most digital designers are accustomed to completing designs comprising several millions of gates by using highly advanced, specialized, and expensive digital-logic design tools. Yet these tools require a great deal of time/effort, which is not practical for analog designers to invest. From a financial and technology perspective, these digital tools are probably seen as "overkill" for designs between 10 and 20 kgates.

To accommodate the digital-logic cells and gates, an analog place-androute methodology was adopted. Conceptually, the adaptation consisted of adding a logic-synthesis step at the front end of an already well-established analog implementation methodology. The netlist was then imported into the Cadence Virtuoso environment. Virtuoso's analog place-androute tools were applied to a standard-cell design. The details of this methodology are shown in Fig. 2.

The specification of the digital-control logic is first captured in RTL Verilog. Next, the Verilog is functionally simulated in NCSim to verify that all functional specifications are met. Once RTL Verilog development is completed,the code is synthesized using standard logic-synthesis tools. Appropriate input and output timing constraints along with estimated output loading are used during synthesis. Clock-tree and scan-chain synthesis also are performed. Afterward, the synthesized netlist functionalityis compared with the original RTL Verilog using standard-logic equivalencychecking tools.

A gate-level netlist is created at the chip level. It includes modules for the analog blocks. Automatic-test-patterngeneration (ATPG) tools, such as Cadence Encounter Test, use this netlist to create ATPG vectors. In addition, a testbench enables simulation in NCSim.