Differential (balanced) topologies are very often used in RF and microwave circuits, and particularly in integrated circuits (ICs), such as MMICs and single-chip receivers. Such circuits are usually impedance matched at the input at a single carrier or local-oscillator (LO) frequency. Unfortunately, manufacturers' data sheets do not always provide the required differential input impedance of the device at the frequency of interest. In such a case, it is necessary to characterize the differential input admittance or impedance of the balanced device prior to impedance matching. Because low-cost commercial vector network analyzers (VNAs) for measuring scattering (S) parameters generally are equipped with two single-ended test ports, an effective approach is needed for characterizing differential devices with a two-port VNA.

Three methods are often considered for solving this problem:

Among these three methods, the third one is certainly the most powerful. Nevertheless, for the design engineer only occasionally confronted with the characterization of differential input impedance of balanced devices in narrowband RF applications, a multiport test system provides unneeded measurement capability and cost.

For such cases, it is possible to use a less-expensive solution based on a two-port VNA (model HP8753D from Agilent), a few additional components, and the classical approach for characterizing a differential amplifier.⁴ This low-cost solution requires only one port of the VNA with the capability of displaying S₁₁ or S₂₂ parameters on the admittance Smith Chart. This method was originally developed for measuring the differential input impedance of the mixer's balanced RF input port on the model UAA2080T single-chip pager receiver manufactured by Philips Semiconductors.⁶ Measurement accuracy was critical in this case, since it impacted both the output power matching of the LNA stage and the 90-deg. relative phase difference between the receiver's in-phase (I) and quadrature (Q) channels. The differential input impedance of the mixer's balanced RF ports was successfully performed at 40.68 and 224 MHz for two different applications. Only the lower-frequency example will be covered here.

According to the Philips Semiconductors applications handbook,⁶ the UAA2080T integrates a mixer in each I and Q channel. The electrical diagram of one of these mixers is reproduced in Fig. 1: a classical double-balanced Gilbert multiplier, operating with balanced drives at the RF and LO ports. Due to the symmetry, these inputs can be characterized by the representation currently used for modelling the input circuit of a differential amplifier.⁴ The most classical equivalent input circuit of a differential amplifier, is the π, (or Δ) input network shown in Fig. 2. To further simplify the calculations, it is wise to consider the admittances of the three elements in Fig. 2. These admittances include Y_ic = Y_n + Y_p which is the common-mode input admittance. For a well-balanced device such as the mixer in Fig. 1, Y_n ≈ Y_p = Y_c, and consequently:

where:

Y_d = the differential input admittance, when Y_c = 0.

Referring to Fig. 2, in the general case (when Y_c ≠ 0), the differential input admittance that must be considered for performing a balanced impedance matching is:

A single-ended VNA cannot measure Y_id directly; nevertheless, an indirect measurement method enables such an instrument to be used. This method consists in first determining the admittances Y_d and Y_c with the two-step measurement process that follows. In the first step, port 1 of the VNA is AC connected to the two differential inputs (Fig. 3). The resultant S´₁₁ parameter yields the common mode input admittance Y_ic:

and consequently,

where:

Y₀ = 20 × 10^-3 O^-1 is both the output admittance of the VNA and the characteristic admittance of the transmission lines between the VNA's output and the calibration plane.

In the second step, port 1 of the VNA is connected to one differential input, while the second is AC short circuited to ground (Fig. 4). The resultant S´´₁₁ parameter yields Y_is:

and consequently:

Expressions 4 and 6 give the values of the elements in Fig. 2:

After substitution of Eqs. 7 and 8 into Eq. 2, the final expression of the differential input admittance can be found as:

The low-cost VNA used for these measurements has the capability to display the parameters S´₁₁ and S´´₁₁ in an admittance Smith Chart (Figs. 7 and 8). The advantage of displaying an S-parameter in an admittance Smith Chart is that according to Eqs. 4 and 6 and ref. 7, this representation yields directly the values of Y_ic and Y_is. Furthermore, when using the VNA's marker functions, admittances Y_ic and Y_is are characterized by their real parts (conductance G), and imaginary parts (susceptance B). (refer to Figs. 7 and 8). Therefore, in order to exploit optimally the VNA data, it is worth expressing the differential input admittance Y_id (Eq. 9) directly with the conductances and the susceptances of Y_ic and Y_is, respectively:

Substituting Y_ic and Y_is into Eq. 9, by the expressions given respectively by Eqs. 10 and 11 yields the real and imaginary parts of the differential input admittance:

Nevertheless, when performing impedance matching, designers typically use the input and output impedances of the load and the generator to be matched, respectively. Therefore, it is worth calculating the differential input impedance:

After inversion of expression 12, one can find the real and imaginary parts of the differential input impedance:

It is important to note that the accuracy of the differential input admittance or impedance calculated with respectively expressions 12 through 15 is strongly dependent on two sources of errors:

1. The imperfection of the AC short circuits produced by the coupling and bypassing capacitors, C_C1, C_C2, and C_BP, respectively, in Figs. 3 and 4.

2. The quality of the calibration performed when using the VNA.

Concerning the first source of error, making an AC short circuit at high frequencies is not a trivial task, especially when the bandwidth is large. Fortunately in the particular case of narrowband matching, this potential issue can be avoided thanks to a technique called "tuned decoupling."^8,9 This technique consists of looking for the decoupling capacitor or decoupling circuit that exhibit the lowest impedance possible for the frequency of interest, for example, a capacitor with a first self-resonant frequency (SRF1) which coincides with the frequency of interest. Another example is a capacitor and the associated wiring self-inductances that form a series resonant tank circuit tuned to the frequency of interest.