Global Positioning System (GPS) receivers are poised to play a critical role in wireless communications as a result of the United States Federal Communications Commission's (FCC's) E911 directive and location based services (LBS) expected to follow on the heels of the mandate. Successful E911/LBS products and services will require solutions with features that can implement GPS in mobile telephones, for low cost, with low power consumption high accuracy, high sensitivity, and good noise immunity.¹

A GPS receiver typically comprises two functions: the radio front end and the baseband digital signal processor (DSP). Complementary-metal-oxide-semiconductor (CMOS) digital technology improvements now allow baseband designs to be ported across silicon vendors and be realized at the system level using reliable processors such as the DSP cores from CEVA (Northampton, England). Ideally, the RF front end would also be available in a standard process and portable across a variety of suppliers.

Support of embedded GPS solutions involves the development of an approach to provide appropriately featured silicon GPS on RF integrated circuit (RF IC) solutions with minimal redesign time. What follows is an explanation of that approach and how software modeling methods were used to evaluate RF IC design compromises, based on the Advanced Design System (ADS) simulator from Agilent Technologies (Santa Rosa, CA).

Radio-receiver design normally breaks down into two aspects: the top or system-level requirements, such as chip gain and frequency planning, and the individual circuit block performance. Traditional design approaches use separate tools for system, DSP, and RF design. RF IC designers typically must reconcile different modelling results of analog, digital, and RF signals in high-density circuits. For example, integrating bipolar transistors alongside passive components and high-speed CMOS logic introduces significant uncertainty in the operational behavior of the circuits, illustrated by the need to model a phase-locked loop (PLL), where the designer is faced with having to co-simulate digital counters/dividers with the analog voltage-controlled oscillator (VCO).

The initial design and development of a GPS radio requires a careful design process focused on the particular and specific attributes of the target process technology. Converting this into intellectual property (IP) for porting to other processes requires an approach that will reduce the development time and cost significantly below that of the original design phase. Indeed, most customers have very short development times that can be typically 50 to 70 percent of the time taken for the first demonstrator design.

As a result, a methodology was needed that would support frequency-domain and mixed-domain simulation technologies; optimization and statistical design tools; and additional device, system, and behavioral models. This methodology would allow both a top down and bottom up approach so that transistor level changes due to the different process models can be transported to the system level. ADS allows the use of both time-domain and harmonic-balance nonlinear simulation techniques.

This approach made it possible to compare the trade-offs of a single-chip GPS receiver on an advanced 0.13-µm CMOS process and a design developed with separate RF and digital chips (allowing the digital IP to be incorporated into a host chip). The software helped determine that overall system performance would benefit from a separate radio on an advanced silicon-germanium (SiGe) BiCMOS process (Fig. 1) The radio design is the XPERT-GPS RF platform (Fig. 2) which provides the radio front end for a GPS developed for use in mobile communications, such as handsets and personal digital assistants (PDAs).

The radio design uses a SiGe bipolar CMOS (SiGe BiCMOS) process to achieve a high level of integration, a noise figure of less than 1.5 dB, low power consumption, and low system implementation cost. The radio downconverts the GPS L1 band at 1575.42 MHz and performs a selectable 1-b sign/magnitude or 2-b-sign/1-b magnitude analog-to-digital (ADC) conversion to produce a baseband signal at 3.78 MHz, which feeds the baseband processor.

A variable frequency plan provides the necessary local oscillator (LO) and baseband clock frequencies using an external temperature-compensated crystal oscillator (TCXO), enabling the use of a single board design for different reference clocks from 10 to 26 MHz. Alternatively, a single crystal may be connected to the device using the built-in oscillator circuitry for applications requiring a lower-cost solution.

Key challenges on the RF subsystem are to achieve the GPS requirements of image rejection simultaneously with the capability for co-operational functionality within a mobile-telephone handset. Coprocessing functionality must address both the hostile RF environment and the need to optimize the scarce resources of space, bandwidth, DC power, processing power, or millions of instructions per second (MIPS in terms of clock cycles) in the presence of interferers generated by the mobile-telephone protocols.

GPS RF models were developed at multiple abstraction levels using ADS to generate and send GPS signals through to a single-channel baseband correlator for demodulation. With this approach, it was possible to define, optimize, and specify the performance of each block for silicon implementation, simplifying the task of porting the design to another semiconductor process. The approach also allows the RF IC IP to be used as a CEVA block in a customer's test bench, thereby reducing the time taken to simulate and derive probable performance in a given system environment.

Figure 3 shows the top-level schematic of the RF IC in the design simulator window. The simulator allows the properties of each block to be displayed so that simulation environment parameters can be easily observed. This is important since each symbol may contain subhierarchy information.

The simulator must be able to model key system performance parameters, including noise, linearity, gain, sensitivity, frequency, and modulation. The power spectral density (PSD) for a typical GPS spectrum is shown in Fig. 4 along with thermal noise. Note the sinx/x nature of the GPS signal. The RF IC must process a signal that is about 20 dB below the noise level; only by performing integration until the signal-to-noise ratio (SNR) is greater than zero can the receiver recover the GPS signal from the noise.