Power lateral diffused metal-oxide-semiconductor (LDMOS) transistors, popularly used in linear high-power amplifiers (HPAs) for cellular base stations, are not without their linearity and stability problems. In addition to long-term threshold drift, stability problems have recently surfaced which include short-term "memory" problems requiring complex and expensive corrective circuitry. To examine these problems more closely, the "hot-electron" problem inherent in all current production LDMOS devices will be investigated and correlated with both short- and long-term device characteristics related to hot electrons. This article will also explore a novel design approach that not only eliminates the hot-electron problem completely, but may also allow a dramatic improvement in device linearity.

The LDMOS threshold drift problem has been discussed for many years. Most of the focus has been on hot electron injection into the gate oxide, causing a drift in the threshold voltage of the LDMOS device,^1-3 changing the idling current, (I_dq), with time. This, in turn, affects the gain, output power, and linearity of the circuit. Recent reports have documented short-term "memory" effects that have proven annoying to RF circuit designers.^4,5 It appears that these short-term effects can be controlled (to some extent) by including a capacitor network in the bias circuit, reducing the nonlinear characteristics of the amplifier. As will be shown, these short-term effects are most likely the result of current/voltage distortion in the transfer characteristics of the device, brought about by driving the LDMOS transistor into secondary breakdown.⁶

The secondary breakdown effect is encountered because of the parasitic bipolar transistor inherent in an LDMOS transistor. The effect is exacerbated by the shallow drain diffusion incorporated into all current commercial devices. The shallow drain is necessary to reduce the Miller capacitance (from gate to drain), which is critical for high-frequency operation. This, in turn, produces very high electric fields in the drain, a result of dropping a high voltage (~28 V) across an extremely narrow distance (~0.4 µm).

Secondary breakdown has long been known as a frequency-dependant effect. This is due to the accumulation of hot electrons into a destructive current of sufficient magnitude to harm the device (over time). For high-frequency silicon power transistors, the current/voltage swing across the drain is sufficiently swift that destruction usually can't occur. However, if the high-frequency device is then used in a low-frequency application, or is modulated with lower-frequency signals at high peak powers, a destructive current has more time to accumulate. Under such conditions, a device could then be damaged and nonlinear power distortion will likely be apparent in the device's output waveforms.

This onset of secondary breakdown is most likely the effect recently described as a "memory" effect.^4,5 In such a case, the electric field in the device is sufficiently high, and the current through the drain is high enough, to trigger secondary breakdown. This results in distorted output waveforms with observable harmonic nonlinearities, although is usually not serious enough to damage the LDMOS device. The device's capacitor network tends to reduce this distortion by attempting to hold the drain current constant. An interesting experiment would be to study the distortion of the LDMOS device at much-lower frequencies, since it is expected that intermodulation distortion (IMD) would increase dramatically under secondary breakdown conditions. For this reason, most production microwave LDMOS devices cannot run safely at frequencies below 100 MHz.

Secondary breakdown is also the reason that all high-frequency power bipolar transistors require emitter ballast resistors—to reduce this effect. Power transistors that operate above several hundred megahertz require these ballast resistors to limit these destructive effects and provide reliable operation. Lower-frequency power transistors (in the kilohertz range) operate reliably without them, simply because they have much wider base widths and much thicker collector regions. The wider bases and thicker collectors (analogous to the drains of a power FET) dramatically lower the electric field in the device, reducing the tendency to be driven into secondary breakdown. Base widths (or channels) of low-frequency devices tend to be many microns in length, compared to fractions of a micron for high-frequency devices. Collectors (drains) in lower-frequency devices are similarly thicker, providing a measure of localized ballast.

A sketch of a typical LDMOS device (Fig. 1) indicates the position and thickness of the drain. The figure also shows a self-aligned shadow-isolated device with a much-thicker epi drain, believed to be free from ALL hot electron effects. Note that the 2.5-µm-thick N-drain epitaxial region and 8-µm-thick P-epitaxial layer reduces the field in a thick-drain LDMOS device by roughly an order of 5 to 10 over a conventional polygate LDMOS device utilizing a shallow diffused drain. The thicker epitaxial drain also allows higher saturated drain current, increasing device linearity at high current.

The electric fields in the two LDMOS devices can be approximated by Fig. 2. The thick-drain device allows for about a 5-to-10-fold reduction in the electric field (due to the much-wider depletion region). This should allow for both an elimination of the threshold shift problem and a dramatic improvement in secondary breakdown characteristics, supporting operation at significantly lower frequencies. This, in turn, should eliminate the long-term threshold drift and short-term memory effects.